Inventor · disambiguated record
Daniel J. Lussier
Also filed as: LUSSIER DANIEL · LUSSIER DANIEL J
16 granted patents·3 pending applications·647 citations·filing 1996–2012
96Inventor score
Files withMINDSPEED TECH INC7MAKER COMMUNICATIONS INC5SUN MICROSYSTEMS INC2CONEXANT SYSTEMS INC1GRAHAM SIMON1
Top patents by PatentIndex Score
19 records- 0193US6760337B1Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levelsMINDSPEED TECH INC·Filed 2000·Granted Jul 6, 2004·68 cites·18 claims
- 0291US8312318B2Systems and methods of high availability cluster environment failover protectionGRAHAM SIMON P·Filed 2012·Granted Nov 13, 2012·29 cites·14 claims
- 0391US6888830B1Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parametersMINDSPEED TECH INC·Filed 2000·Granted May 3, 2005·53 cites·18 claims
- 0491US6754223B1Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processorMINDSPEED TECH INC·Filed 2000·Granted Jun 22, 2004·54 cites·8 claims
- 0586US8234521B2Systems and methods for maintaining lock step operationGRAHAM SIMON·Filed 2008·Granted Jul 31, 2012·18 cites·13 claims
- 0686US5748631AAsynchronous transfer mode cell processing system with multiple cell source multiplexingMAKER COMMUNICATIONS INC·Filed 1996·Granted May 5, 1998·180 cites·9 claims
- 0785US7046686B1Integrated circuit that processes communication packets with a buffer management engine having a pointer cacheMINDSPEED TECH INC·Filed 2000·Granted May 16, 2006·28 cites·31 claims
- 0885US6359891B1Asynchronous transfer mode cell processing system with scoreboard schedulingCONEXANT SYSTEMS INC·Filed 2000·Granted Mar 19, 2002·40 cites·20 claims
- 0984US6804239B1Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context informationMINDSPEED TECH INC·Filed 2000·Granted Oct 12, 2004·27 cites·8 claims
- 1082US6822959B2Enhancing performance by pre-fetching and caching data directly in a communication processor's register setMINDSPEED TECH INC·Filed 2001·Granted Nov 23, 2004·34 cites·7 claims
- 1178USRE42092EIntegrated circuit that processes communication packets with a buffer management engine having a pointer cacheTOMPKINS JOSEPH B·Filed 2008·Granted Feb 1, 2011·6 cites·66 claims
- 1274US7099328B2Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing taskMINDSPEED TECH INC·Filed 2001·Granted Aug 29, 2006·13 cites·8 claims
- 1364US6128303AAsynchronous transfer mode cell processing system with scoreboard schedulingMAKER COMMUNICATIONS INC·Filed 1996·Granted Oct 3, 2000·48 cites·44 claims
- 1454US5748630AAsynchronous transfer mode cell processing system with load multiple instruction and memory write-backMAKER COMMUNICATIONS INC·Filed 1996·Granted May 5, 1998·33 cites·12 claims
- 1548US2005060414A1Object-aware transport-layer network processing engineSUN MICROSYSTEMS INC·Filed 2004·Application pending·0 cites
- 1648US2005060427A1Object-aware transport-layer network processing engineSUN MICROSYSTEMS INC·Filed 2004·Application pending·0 cites
- 1745US2004210663A1Object-aware transport-layer network processing engineFiled 2003·Application pending·0 cites
- 1842US5860148AAsynchronous transfer mode cell processing system with cell buffer space gatheringMAKER COMMUNICATIONS INC·Filed 1996·Granted Jan 12, 1999·7 cites·21 claims
- 1936US5794025AMethod and device for performing modulo-based arithmetic operations in an asynchronous transfer mode cell processing systemMAKER COMMUNICATIONS INC·Filed 1996·Granted Aug 11, 1998·9 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →