Inventor · disambiguated record
Keisuke Hirabayashi
Also filed as: HIRABAYASHI KEISUKE
4 granted patents·2 pending applications·21 citations·filing 2004–2012
73Inventor score
Files withRENESAS ELECTRONICS CORP2HIRABAYASHI KEISUKE1ISHIDA MAKOTO1NAT UNIV CORP TOYOHASHI UNIV T1NEC ELECTRONICS CORP1
Top patents by PatentIndex Score
6 records- 0183US7900177B2Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor deviceRENESAS ELECTRONICS CORP·Filed 2008·Granted Mar 1, 2011·13 cites·17 claims
- 0260US8181142B2Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor deviceHIRABAYASHI KEISUKE·Filed 2010·Granted May 15, 2012·2 cites·5 claims
- 0359US8365127B2Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor deviceRENESAS ELECTRONICS CORP·Filed 2012·Granted Jan 29, 2013·1 cites·8 claims
- 0445US7692257B2Ultrasonic sensor comprising a metal/ferroelectric/metal/insulator/semiconductor structureNAT UNIV CORP TOYOHASHI UNIV T·Filed 2004·Granted Apr 6, 2010·5 cites·6 claims
- 0544US2010131915A1Method, device, and program for predicting a manufacturing defect part of a semiconductor deviceNEC ELECTRONICS CORP·Filed 2009·Application pending·0 cites
- 0635US2009278212A1Integrated DeviceISHIDA MAKOTO·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →