Inventor · disambiguated record
David S. Collins
Also filed as: COLLINS DAVID · COLLINS DAVID S
37 granted patents·6 pending applications·933 citations·filing 1995–2018
98Inventor score
Top patents by PatentIndex Score
43 records- 0198US6096728AComposition and method for treating inflammatory diseasesAMGEN INC·Filed 1997·Granted Aug 1, 2000·322 cites·20 claims
- 0296US6733753B2Composition and method for treating inflammatory diseasesAMGEN INC·Filed 2001·Granted May 11, 2004·73 cites·16 claims
- 0395US8674423B2Semiconductor structure having vias and high density capacitorsCOLLINS DAVID S·Filed 2011·Granted Mar 18, 2014·26 cites·18 claims
- 0494US6294170B1Composition and method for treating inflammatory diseasesAMGEN INC·Filed 1998·Granted Sep 25, 2001·122 cites·15 claims
- 0592US10170476B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2017·Granted Jan 1, 2019·5 cites·19 claims
- 0691US7498622B1Latchup robust gate array using through wafer viaIBM·Filed 2007·Granted Mar 3, 2009·23 cites·14 claims
- 0790US7943445B2Asymmetric junction field effect transistorIBM·Filed 2009·Granted May 17, 2011·16 cites·10 claims
- 0890US6355267B1Liposome preparation and material encapsulation methodAMGEN INC·Filed 1997·Granted Mar 12, 2002·103 cites·16 claims
- 0987US9842838B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2016·Granted Dec 12, 2017·3 cites·19 claims
- 1087US5874075AStable protein: phospholipid compositions and methodsAMGEN INC·Filed 1995·Granted Feb 23, 1999·88 cites·42 claims
- 1185US8017471B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2008·Granted Sep 13, 2011·7 cites·19 claims
- 1283US9397010B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2016·Granted Jul 19, 2016·2 cites·18 claims
- 1383US8288244B2Lateral passive device having dual annular electrodesCOLLINS DAVID S·Filed 2010·Granted Oct 16, 2012·6 cites·4 claims
- 1483US7549135B2Design methodology of guard ring design resistance optimization for latchup preventionIBM·Filed 2006·Granted Jun 16, 2009·13 cites·2 claims
- 1582US8169007B2Asymmetric junction field effect transistorANDERSON FREDERICK G·Filed 2011·Granted May 1, 2012·6 cites·15 claims
- 1682US8089126B2Method and structures for improving substrate loss and linearity in SOI substratesBOTULA ALAN BERNARD·Filed 2009·Granted Jan 3, 2012·9 cites·5 claims
- 1780US5567433ALiposome preparation and material encapsulation methodAMGEN INC·Filed 1995·Granted Oct 22, 1996·54 cites·6 claims
- 1879US8101494B2Structure, design structure and method of manufacturing a structure having VIAS and high density capacitorsCOLLINS DAVID S·Filed 2008·Granted Jan 24, 2012·7 cites·24 claims
- 1977US7134099B2ESD design, verification and checking system and method of useIBM·Filed 2003·Granted Nov 7, 2006·25 cites·31 claims
- 2075US8008748B2Deep trench varactorsIBM·Filed 2008·Granted Aug 30, 2011·6 cites·29 claims
- 2172US9275997B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2014·Granted Mar 1, 2016·1 cites·20 claims
- 2270US8853789B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2013·Granted Oct 7, 2014·1 cites·6 claims
- 2368US8234606B2Metal wiring structure for integration with through substrate viasCOLLINS DAVID S·Filed 2011·Granted Jul 31, 2012·2 cites·20 claims
- 2467US7442996B2Structure and method for enhanced triple well latchup robustnessIBM·Filed 2006·Granted Oct 28, 2008·3 cites·14 claims
- 2565US10978452B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2018·Granted Apr 13, 2021·0 cites·18 claims
- 2665US8420518B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryCHAPMAN PHILLIP F·Filed 2011·Granted Apr 16, 2013·1 cites·13 claims
- 2764US8138607B2Metal fill structures for reducing parasitic capacitanceCOLLINS DAVID S·Filed 2009·Granted Mar 20, 2012·3 cites·20 claims
- 2864US7968975B2Metal wiring structure for integration with through substrate viasIBM·Filed 2008·Granted Jun 28, 2011·2 cites·25 claims
- 2958US7855420B2Structure for a latchup robust array I/O using through wafer viaIBM·Filed 2008·Granted Dec 21, 2010·1 cites·11 claims
- 3057US7739636B2Design structure incorporating semiconductor device structures that shield a bond pad from electrical noiseIBM·Filed 2007·Granted Jun 15, 2010·1 cites·7 claims
- 3157US7696541B2Structure for a latchup robust gate array using through wafer viaIBM·Filed 2008·Granted Apr 13, 2010·1 cites·9 claims
- 3256US7868423B2Optimized device isolationIBM·Filed 2008·Granted Jan 11, 2011·1 cites·19 claims
- 3352US2008265333A1Structure and method for enhanced triple well latchup robustnessIBM·Filed 2008·Application pending·0 cites
- 3448US2008142861A1Symmetric capacitor structureCOLLINS DAVID S·Filed 2008·Application pending·0 cites
- 3547US2009166798A1Design methodology for guard ring design resistance optimization for latchup preventionIBM·Filed 2007·Application pending·0 cites
- 3646US7821097B2Lateral passive device having dual annular electrodesIBM·Filed 2006·Granted Oct 26, 2010·0 cites·4 claims
- 3746US7402890B2Method for symmetric capacitor formationIBM·Filed 2006·Granted Jul 22, 2008·0 cites·10 claims
- 3844US2009020856A1Semiconductor device structures and methods for shielding a bond pad from electrical noiseIBM·Filed 2007·Application pending·0 cites
- 3943US8288821B2SOI (silicon on insulator) substrate improvementsBOTULA ALAN BERNARD·Filed 2009·Granted Oct 16, 2012·0 cites·20 claims
- 4043US8125013B2Structure, design structure and method of manufacturing a structure having VIAS and high density capacitorsCOLLINS DAVID S·Filed 2008·Granted Feb 28, 2012·0 cites·24 claims
- 4143US7741681B2Latchup robust array I/O using through wafer viaIBM·Filed 2007·Granted Jun 22, 2010·0 cites·18 claims
- 4241US2008149983A1Metal-oxide-semiconductor (mos) varactors and methods of forming mos varactorsIBM·Filed 2006·Application pending·0 cites
- 4339US2007205430A1Method and structure of refractory metal reach through in bipolar transistorCOLLINS DAVID S·Filed 2006·Application pending·0 cites
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