Inventor · disambiguated record
Anda C. Mocuta
Also filed as: MOCUTA ANDA · MOCUTA ANDA C
28 granted patents·7 pending applications·909 citations·filing 2000–2022
97Inventor score
Top patents by PatentIndex Score
35 records- 0198US7723750B2MOSFET with super-steep retrograded islandIBM·Filed 2007·Granted May 25, 2010·124 cites·15 claims
- 0298US6881635B1Strained silicon NMOS devices with embedded source/drainIBM·Filed 2004·Granted Apr 19, 2005·176 cites·13 claims
- 0397US6916698B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2004·Granted Jul 12, 2005·139 cites·8 claims
- 0493US6762469B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2002·Granted Jul 13, 2004·68 cites·5 claims
- 0592US7067400B2Method for preventing sidewall consumption during oxidation of SGOI islandsIBM·Filed 2004·Granted Jun 27, 2006·62 cites·24 claims
- 0692US6303450B1CMOS device structures and method of making sameIBM·Filed 2000·Granted Oct 16, 2001·67 cites·15 claims
- 0789US7705345B2High performance strained silicon FinFETs device and method for forming sameIBM·Filed 2004·Granted Apr 27, 2010·52 cites·18 claims
- 0889US7691698B2Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drainIBM·Filed 2006·Granted Apr 6, 2010·15 cites·20 claims
- 0989US7560326B2Silicon/silcion germaninum/silicon body device with embedded carbon dopantIBM·Filed 2006·Granted Jul 14, 2009·18 cites·2 claims
- 1088US6746924B1Method of forming asymmetric extension mosfet using a drain side spacerIBM·Filed 2003·Granted Jun 8, 2004·45 cites·13 claims
- 1187US8626480B2Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factorsCHANG PAUL·Filed 2009·Granted Jan 7, 2014·20 cites·23 claims
- 1285US6509241B2Process for fabricating an MOS device having highly-localized halo regionsIBM·Filed 2000·Granted Jan 21, 2003·35 cites·19 claims
- 1384US8239790B2Methods and system for analysis and management of parametric yieldCULP JAMES A·Filed 2011·Granted Aug 7, 2012·4 cites·20 claims
- 1483US7056782B2CMOS silicide metal gate integrationIBM·Filed 2004·Granted Jun 6, 2006·25 cites·19 claims
- 1581US7411227B2CMOS silicide metal gate integrationIBM·Filed 2006·Granted Aug 12, 2008·7 cites·16 claims
- 1681US7268049B2Structure and method for manufacturing MOSFET with super-steep retrograded islandIBM·Filed 2004·Granted Sep 11, 2007·21 cites·7 claims
- 1774US7655557B2CMOS silicide metal gate integrationIBM·Filed 2008·Granted Feb 2, 2010·4 cites·9 claims
- 1871US9639652B2Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factorsGLOBALFOUNDRIES INC·Filed 2014·Granted May 2, 2017·2 cites·26 claims
- 1970US7879650B2Method of providing protection against charging damage in hybrid orientation transistorsIBM·Filed 2007·Granted Feb 1, 2011·3 cites·9 claims
- 2069US8168971B2Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drainCHIDAMBARRAO DURESETI·Filed 2008·Granted May 1, 2012·3 cites·20 claims
- 2169US6635517B2Use of disposable spacer to introduce gettering in SOI layerIBM·Filed 2001·Granted Oct 21, 2003·13 cites·25 claims
- 2268US8754412B2Intra die variation monitor using through-silicon viaYU XIAOJUN·Filed 2012·Granted Jun 17, 2014·2 cites·7 claims
- 2366US8429576B2Methods and system for analysis and management of parametric yieldCULP JAMES A·Filed 2012·Granted Apr 23, 2013·1 cites·20 claims
- 2465US8042070B2Methods and system for analysis and management of parametric yieldIBM·Filed 2007·Granted Oct 18, 2011·3 cites·20 claims
- 2556US8997028B2Methods and system for analysis and management of parametric yieldMENTOR GRAPHICS CORP·Filed 2013·Granted Mar 31, 2015·0 cites·8 claims
- 2654US7928513B2Protection against charging damage in hybrid orientation transistorsIBM·Filed 2008·Granted Apr 19, 2011·0 cites·9 claims
- 2752US2024030219A1Logic gatesMICRON TECHNOLOGY INC·Filed 2022·Application pending·0 cites
- 2849US7492016B2Protection against charging damage in hybrid orientation transistorsIBM·Filed 2006·Granted Feb 17, 2009·0 cites·5 claims
- 2948US2005242340A1Strained silicon NMOS devices with embedded source/drainIBM·Filed 2005·Application pending·0 cites
- 3047US2023329612A1Determining driver capabilityMICRON TECHNOLOGY INC·Filed 2022·Application pending·0 cites
- 3144US2008179636A1N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layersIBM·Filed 2007·Application pending·0 cites
- 3241US2006220112A1Semiconductor device forming method and structure for retarding dopant-enhanced diffusionIBM·Filed 2005·Application pending·0 cites
- 3341US2006151787A1LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTIONIBM·Filed 2005·Application pending·0 cites
- 3439US8106462B2Balancing NFET and PFET performance using straining layersCHEN XIANGDONG·Filed 2010·Granted Jan 31, 2012·0 cites·20 claims
- 3535US2002142526A1Structures and methods to minimize plasma charging damage in silicon on insulator devicesIBM·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →