Inventor · disambiguated record
Hing Y. To
Also filed as: TO HING · TO HING Y · TO HING YAN
29 granted patents·1 pending application·408 citations·filing 1998–2024
97Inventor score
Top patents by PatentIndex Score
30 records- 0193US10860776B1Printed circuit board (PCB) modular designXILINX INC·Filed 2019·Granted Dec 8, 2020·19 cites·20 claims
- 0292US7459938B2Method and apparatus for power efficient and scalable memory interfaceINTEL CORP·Filed 2006·Granted Dec 2, 2008·26 cites·5 claims
- 0389US7602859B2Calibrating integrating receivers for source synchronous protocolINTEL CORP·Filed 2005·Granted Oct 13, 2009·22 cites·27 claims
- 0489US7401246B2Nibble de-skew method, apparatus, and systemINTEL CORP·Filed 2005·Granted Jul 15, 2008·19 cites·17 claims
- 0587US7388795B1Modular memory controller clocking architectureINTEL CORP·Filed 2006·Granted Jun 17, 2008·15 cites·20 claims
- 0687US6885959B2Circuit and method for calibrating DRAM pullup Ron to pulldown RonINTEL CORP·Filed 2002·Granted Apr 26, 2005·35 cites·44 claims
- 0785US6747483B2Differential memory interface systemINTEL CORP·Filed 2002·Granted Jun 8, 2004·29 cites·21 claims
- 0884US7194559B2Slave I/O driver calibration using error-nulling master referenceINTEL CORP·Filed 2002·Granted Mar 20, 2007·38 cites·14 claims
- 0983US6771515B2Systems having modules with on die terminationsINTEL CORP·Filed 2001·Granted Aug 3, 2004·29 cites·23 claims
- 1080US6941484B2Synthesis of a synchronization clockINTEL CORP·Filed 2002·Granted Sep 6, 2005·29 cites·30 claims
- 1178US6051999ALow voltage programmable complementary input stage sense amplifierINTEL CORP·Filed 1998·Granted Apr 18, 2000·48 cites·17 claims
- 1276US7692457B2Dual-path clocking architectureINTEL CORP·Filed 2008·Granted Apr 6, 2010·8 cites·20 claims
- 1376US6725390B1Method and an apparatus for adjusting clock signal to sample dataINTEL CORP·Filed 2000·Granted Apr 20, 2004·20 cites·15 claims
- 1464US11428733B1On-die virtual probes (ODVP) for integrated circuitriesXILINX INC·Filed 2021·Granted Aug 30, 2022·0 cites·20 claims
- 1563US7334148B2Optimization of integrated circuit device I/O bus timingINTEL CORP·Filed 2004·Granted Feb 19, 2008·7 cites·9 claims
- 1663US7245682B2Determining an optimal sampling clockINTEL CORP·Filed 2002·Granted Jul 17, 2007·8 cites·5 claims
- 1762US7324403B2Latency normalization by balancing early and late clocksINTEL CORP·Filed 2004·Granted Jan 29, 2008·8 cites·30 claims
- 1862US6507218B1Method and apparatus for reducing back-to-back voltage glitch on high speed data busINTEL CORP·Filed 2000·Granted Jan 14, 2003·9 cites·18 claims
- 1961US6597202B1Systems with skew control between clock and data signalsINTEL CORP·Filed 2001·Granted Jul 22, 2003·9 cites·28 claims
- 2060US6724082B2Systems having modules with selectable on die terminationsINTEL CORP·Filed 2001·Granted Apr 20, 2004·8 cites·25 claims
- 2160US2025147844A1Error Alert Encoding for Improved Error MitigationADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 2259US7805627B2Clock synchronization scheme for deskewing operations in a data interfaceINTEL CORP·Filed 2007·Granted Sep 28, 2010·1 cites·10 claims
- 2357US7243176B2Method and apparatus for power efficient and scalable memory interfaceINTEL CORP·Filed 2004·Granted Jul 10, 2007·7 cites·28 claims
- 2453US7954001B2Nibble de-skew method, apparatus, and systemINTEL CORP·Filed 2008·Granted May 31, 2011·0 cites·20 claims
- 2553US7010637B2Single-ended memory interface systemINTEL CORP·Filed 2002·Granted Mar 7, 2006·6 cites·16 claims
- 2652US12476193B2Routing a communication bus within multiple layers of a printed circuit boardXILINX INC·Filed 2021·Granted Nov 18, 2025·0 cites·18 claims
- 2748US6631083B2Systems with modules and clocking thereforeINTEL CORP·Filed 2001·Granted Oct 7, 2003·5 cites·29 claims
- 2845US6973603B2Method and apparatus for optimizing timing for a multi-drop busINTEL CORP·Filed 2002·Granted Dec 6, 2005·3 cites·18 claims
- 2940US7117401B2Method and apparatus for optimizing timing for a multi-drop busINTEL CORP·Filed 2005·Granted Oct 3, 2006·0 cites·20 claims
- 3037US7446572B2Method and system for a configurable Vcc reference and Vss reference differential current mode transmitterINTEL CORP·Filed 2005·Granted Nov 4, 2008·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →