Inventor · disambiguated record
Vimal Reddy
Also filed as: REDDY VIMAL · REDDY VIMAL K · REDDY VIMAL KODANDARAMA
9 granted patents·6 pending applications·42 citations·filing 2009–2024
86Inventor score
Top patents by PatentIndex Score
15 records- 0196US11016810B1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2020·Granted May 25, 2021·15 cites·15 claims
- 0294US11360932B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 14, 2022·5 cites·18 claims
- 0391US10521395B1Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Dec 31, 2019·6 cites·16 claims
- 0488US12013807B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2022·Granted Jun 18, 2024·1 cites·18 claims
- 0586US10606797B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Mar 31, 2020·3 cites·12 claims
- 0681US12461888B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2024·Granted Nov 4, 2025·0 cites·16 claims
- 0778US2024311194A1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2024·Application pending·0 cites
- 0871US8521962B2Managing counter saturation in a filterREDDY VIMAL K·Filed 2009·Granted Aug 27, 2013·12 cites·66 claims
- 0969US12014214B2Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2021·Granted Jun 18, 2024·0 cites·19 claims
- 1049US9317293B2Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Granted Apr 19, 2016·0 cites·28 claims
- 1143US2014281439A1Hardware optimization of hard-to-predict short forward branchesQUALCOMM INC·Filed 2013·Application pending·0 cites
- 1236US2013346727A1Methods and Apparatus to Extend Software Branch Target HintsREDDY VIMAL K·Filed 2012·Application pending·0 cites
- 1336US2016350116A1Mitigating wrong-path effects in branch predictionQUALCOMM INC·Filed 2015·Application pending·0 cites
- 1435US2017083333A1Branch target instruction cache (btic) to store a conditional branch instructionQUALCOMM INC·Filed 2015·Application pending·0 cites
- 1531US2016335089A1Eliminating redundancy in a branch target instruction cache by establishing entries using the target address of a subroutineQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →