Inventor · disambiguated record
Jowei Dun
Also filed as: DUN JOWEI
17 granted patents·1,059 citations·filing 1992–2018
95Inventor score
Files withTAIWAN SEMICONDUCTOR MFG8SILICONIX INC4ALPHA & OMEGA SEMICONDUCTOR2ALPHA & OMEGA SEMICONDUCTOR INCORPORATED2INTEGRATED DEVICE TECH1
Top patents by PatentIndex Score
17 records- 0196US5757081ASurface mount and flip chip technology for total integrated circuit isolationSILICONIX INC·Filed 1996·Granted May 26, 1998·224 cites·8 claims
- 0295US5753529ASurface mount and flip chip technology for total integrated circuit isolationSILICONIX INC·Filed 1995·Granted May 19, 1998·183 cites·7 claims
- 0394US5767578ASurface mount and flip chip technology with diamond film passivation for total integated circuit isolationSILICONIX INC·Filed 1996·Granted Jun 16, 1998·176 cites·19 claims
- 0490US6291872B1Three-dimensional type inductor for mixed mode radio frequency deviceTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 18, 2001·99 cites·19 claims
- 0587US10020380B2Power device with high aspect ratio trench contacts and submicron pitches between trenchesALPHA & OMEGA SEMICONDUCTOR INCORPORATED·Filed 2015·Granted Jul 10, 2018·5 cites·10 claims
- 0687US6291331B1Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issueTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 18, 2001·111 cites·21 claims
- 0786US5956609AMethod for reducing stress and improving step-coverage of tungsten interconnects and plugsTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Sep 21, 1999·106 cites·14 claims
- 0885US9691863B2Self-aligned contact for trench power MOSFETALPHA & OMEGA SEMICONDUCTOR·Filed 2015·Granted Jun 27, 2017·4 cites·8 claims
- 0984US6099662AProcess for cleaning a semiconductor substrate after chemical-mechanical polishingTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 8, 2000·77 cites·42 claims
- 1077US10644118B2Self-aligned contact for trench power MOSFETALPHA & OMEGA SEMICONDUCTOR·Filed 2017·Granted May 5, 2020·2 cites·11 claims
- 1172US10424654B2Power device with high aspect ratio trench contacts and submicron pitches between trenchesALPHA & OMEGA SEMICONDUCTOR INCORPORATED·Filed 2018·Granted Sep 24, 2019·1 cites·13 claims
- 1260US6479881B2Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitryTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Nov 12, 2002·6 cites·2 claims
- 1358US6268274B1Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitryTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jul 31, 2001·19 cites·19 claims
- 1449US6281146B1Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformityTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 28, 2001·14 cites·17 claims
- 1546US5904525AFabrication of high-density trench DMOS using sidewall spacersSILICONIX INC·Filed 1996·Granted May 18, 1999·13 cites·37 claims
- 1642US6395635B1Reduction of tungsten damascene residueTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 28, 2002·9 cites·26 claims
- 1739US5284800AMethod for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor processINTEGRATED DEVICE TECH·Filed 1992·Granted Feb 8, 1994·10 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →