Inventor · disambiguated record
Chanh Tran
Also filed as: JOHNSON MARK · TRAN CHANH · TRAN CHANH V · TRAN CHANH VI
20 granted patents·1,040 citations·filing 1997–2016
96Inventor score
Top patents by PatentIndex Score
20 records- 0199US6539072B1Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2000·Granted Mar 25, 2003·263 cites·31 claims
- 0299US6125157ADelay-locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 1997·Granted Sep 26, 2000·382 cites·20 claims
- 0394US6643752B1Transceiver with latency alignment circuitryRAMBUS INC·Filed 1999·Granted Nov 4, 2003·164 cites·25 claims
- 0492US7065622B2Transceiver with latency alignment circuitryRAMBUS INC·Filed 2005·Granted Jun 20, 2006·24 cites·29 claims
- 0591US7039147B2Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2003·Granted May 2, 2006·34 cites·62 claims
- 0690US7308065B2Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2006·Granted Dec 11, 2007·15 cites·19 claims
- 0786US7124270B2Transceiver with latency alignment circuitryRAMBUS INC·Filed 2005·Granted Oct 17, 2006·11 cites·24 claims
- 0883US9870982B2Distributed on-chip decoupling apparatus and method using package interconnectRAMBUS INC·Filed 2016·Granted Jan 16, 2018·3 cites·19 claims
- 0981US5959481ABus driver circuit including a slew rate indicator circuit having a one shot circuitRAMBUS INC·Filed 1997·Granted Sep 28, 1999·97 cites·18 claims
- 1076US9006907B2Distributed on-chip decoupling apparatus and method using package interconnectRAMBUS INC·Filed 2013·Granted Apr 14, 2015·3 cites·11 claims
- 1172US6819137B1Technique for voltage level shifting in input circuitryRAMBUS INC·Filed 2002·Granted Nov 16, 2004·12 cites·24 claims
- 1269US8086812B2Transceiver with latency alignment circuitryDONNELLY KEVIN·Filed 2006·Granted Dec 27, 2011·4 cites·36 claims
- 1369US7088127B2Adaptive impedance output driver circuitRAMBUS INC·Filed 2003·Granted Aug 8, 2006·13 cites·33 claims
- 1460US6809569B2Circuit, apparatus and method having a cross-coupled load with current mirrorsRAMBUS INC·Filed 2002·Granted Oct 26, 2004·12 cites·12 claims
- 1552US9466568B2Distributed on-chip decoupling apparatus and method using package interconnectRAMBUS INC·Filed 2015·Granted Oct 11, 2016·0 cites·16 claims
- 1652US7010658B2Transceiver with latency alignment circuitryRAMBUS INC·Filed 2003·Granted Mar 7, 2006·1 cites·32 claims
- 1749US8458426B2Transceiver with latency alignment circuitryDONNELLY KEVIN·Filed 2007·Granted Jun 4, 2013·0 cites·36 claims
- 1847US8378699B2Self-test method for interface circuitRAMBUS INC·Filed 2009·Granted Feb 19, 2013·1 cites·15 claims
- 1946US7535242B2Interface test circuitRAMBUS INC·Filed 2006·Granted May 19, 2009·1 cites·26 claims
- 2033US6803823B2Circuit, apparatus and method for an adaptive voltage swing limiterRAMBUS INC·Filed 2002·Granted Oct 12, 2004·0 cites·29 claims
Join the waitlist — get patent alerts
Get an alert when Chanh Tran files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →