Inventor · disambiguated record
Kimberly M. Fernsler
Also filed as: FERNSLER KIMBERLY · FERNSLER KIMBERLY M · FERNSLER KIMBERLY MARIE
21 granted patents·2 pending applications·189 citations·filing 2003–2023
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
23 records- 0196US10037211B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2016·Granted Jul 31, 2018·15 cites·17 claims
- 0293US7284112B2Multiple page size address translation incorporating page size predictionIBM·Filed 2005·Granted Oct 16, 2007·35 cites·1 claims
- 0392US11755324B2Gather buffer management for unaligned and gather load operationsIBM·Filed 2021·Granted Sep 12, 2023·2 cites·19 claims
- 0489US7159095B2Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) tableIBM·Filed 2003·Granted Jan 2, 2007·62 cites·4 claims
- 0586US7302527B2Systems and methods for executing load instructions that avoid order violationsIBM·Filed 2004·Granted Nov 27, 2007·47 cites·32 claims
- 0674US10564978B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2018·Granted Feb 18, 2020·1 cites·14 claims
- 0773US7739477B2Multiple page size address translation incorporating page size predictionIBM·Filed 2007·Granted Jun 15, 2010·5 cites·27 claims
- 0871US8898667B2Dynamically manage applications on a processing systemDO LYDIA MAI·Filed 2008·Granted Nov 25, 2014·5 cites·17 claims
- 0971US8387050B2System and method to dynamically manage applications on a processing systemIBM·Filed 2008·Granted Feb 26, 2013·5 cites·18 claims
- 1070US12411688B2Gather buffer management for unaligned and gather load operationsIBM·Filed 2023·Granted Sep 9, 2025·0 cites·18 claims
- 1164US7376816B2Method and systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2004·Granted May 20, 2008·8 cites·7 claims
- 1263US7769985B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2008·Granted Aug 3, 2010·2 cites·9 claims
- 1363US7730290B2Systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2008·Granted Jun 1, 2010·2 cites·13 claims
- 1459US11687337B2Processor overriding of a false load-hit-store detectionIBM·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 1559US11321088B2Tracking load and store instructions and addresses in an out-of-order processorIBM·Filed 2020·Granted May 3, 2022·0 cites·25 claims
- 1658US11314510B2Tracking load and store instructions and addresses in an out-of-order processorIBM·Filed 2020·Granted Apr 26, 2022·0 cites·25 claims
- 1754US11379241B2Handling oversize store to load forwarding in a processorIBM·Filed 2020·Granted Jul 5, 2022·0 cites·19 claims
- 1854US11263151B2Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operationsIBM·Filed 2020·Granted Mar 1, 2022·0 cites·20 claims
- 1953US10884740B2Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threadsIBM·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 2048US7689776B2Method and system for efficient cache locking mechanismTOSHIBA KK·Filed 2005·Granted Mar 30, 2010·0 cites·14 claims
- 2147US9916245B2Accessing partial cachelines in a data cacheIBM·Filed 2016·Granted Mar 13, 2018·0 cites·17 claims
- 2246US2010146214A1Method and system for efficient cache locking mechanismOSANAI TAKEKI·Filed 2010·Application pending·0 cites
- 2345US2005182912A1Method of effective to real address translation for a multi-threaded microprocessorIBM·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →