Inventor · disambiguated record
Stephen G. Jamison
Also filed as: JAMISON STEPHEN G
10 granted patents·1 pending application·319 citations·filing 1995–2011
92Inventor score
Top patents by PatentIndex Score
11 records- 0195US7777522B2Clocked single power supply level shifterFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Aug 17, 2010·53 cites·20 claims
- 0291US8446176B1Reconfigurable engineering change order base cellYANG JIANAN·Filed 2011·Granted May 21, 2013·35 cites·21 claims
- 0380US8575962B2Integrated circuit having critical path voltage scaling and method thereforYANG JIANAN·Filed 2011·Granted Nov 5, 2013·7 cites·15 claims
- 0480US5744841ASemiconductor device with ESD protectionMOTOROLA INC·Filed 1997·Granted Apr 28, 1998·41 cites·23 claims
- 0578US6046897ASegmented bus architecture (SBA) for electrostatic discharge (ESD) protectionMOTOROLA INC·Filed 1997·Granted Apr 4, 2000·43 cites·22 claims
- 0677US5917336ACircuit for electrostatic discharge (ESD) protectionMOTOROLA INC·Filed 1997·Granted Jun 29, 1999·41 cites·18 claims
- 0765US5733794AProcess for forming a semiconductor device with ESD protectionMOTOROLA INC·Filed 1995·Granted Mar 31, 1998·22 cites·20 claims
- 0864US5773326AMethod of making an SOI integrated circuit with ESD protectionMOTOROLA INC·Filed 1996·Granted Jun 30, 1998·31 cites·13 claims
- 0964US5661082AProcess for forming a semiconductor device having a bond padMOTOROLA INC·Filed 1995·Granted Aug 26, 1997·30 cites·16 claims
- 1050US5814893ASemiconductor device having a bond padMOTOROLA INC·Filed 1997·Granted Sep 29, 1998·16 cites·15 claims
- 1136US2009302885A1Two transistor tie circuit with body biasingYANG JIANAN·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →