Inventor · disambiguated record
Andrew F. Glew
Also filed as: GLEW ANDREW · GLEW ANDREW F · GLEW ANDREW FORSYTH
120 granted patents·11 pending applications·6,206 citations·filing 1993–2017
99Inventor score
Top patents by PatentIndex Score
131 records- 0198US8943313B2Fine-grained security in federated data setsGLEW ANDREW F·Filed 2011·Granted Jan 27, 2015·97 cites·50 claims
- 0296US5721855AMethod for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder bufferINTEL CORP·Filed 1996·Granted Feb 24, 1998·335 cites·23 claims
- 0395US9170843B2Data handling apparatus adapted for scheduling operations according to resource allocation based on entitlementGERRITY DANIEL A·Filed 2011·Granted Oct 27, 2015·33 cites·34 claims
- 0495US8955111B2Instruction set adapted for security risk monitoringGLEW ANDREW F·Filed 2011·Granted Feb 10, 2015·32 cites·39 claims
- 0594US9443085B2Intrusion detection using taint accumulationGERRITY DANIEL A·Filed 2011·Granted Sep 13, 2016·25 cites·42 claims
- 0694US8813085B2Scheduling threads based on priority utilizing entitlement vectors, weight and usage levelGLEW ANDREW F·Filed 2011·Granted Aug 19, 2014·24 cites·24 claims
- 0794US8028152B2Hierarchical multi-threading processor for executing virtual threads in a time-multiplexed fashionINVENTION SCIENCE FUND I LLC·Filed 2007·Granted Sep 27, 2011·28 cites·20 claims
- 0893US8930714B2Encrypted memoryGLEW ANDREW F·Filed 2011·Granted Jan 6, 2015·36 cites·47 claims
- 0991US9575903B2Security perimeterGERRITY DANIEL A·Filed 2011·Granted Feb 21, 2017·15 cites·48 claims
- 1091US9460290B2Conditional security response using taint vector monitoringGERRITY DANIEL A·Filed 2011·Granted Oct 4, 2016·17 cites·47 claims
- 1191US9098608B2Processor configured to allocate resources using an entitlement vectorGLEW ANDREW F·Filed 2011·Granted Aug 4, 2015·15 cites·32 claims
- 1289US9798873B2Processor operable to ensure code integrityGERRITY DANIEL A·Filed 2011·Granted Oct 24, 2017·13 cites·29 claims
- 1389US5956753AMethod and apparatus for handling speculative memory access operationsINTEL CORP·Filed 1997·Granted Sep 21, 1999·142 cites·31 claims
- 1489US5852726AMethod and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced mannerINTEL CORP·Filed 1995·Granted Dec 22, 1998·163 cites·107 claims
- 1589US5751996AMethod and apparatus for processing memory-type information within a microprocessorINTEL CORP·Filed 1996·Granted May 12, 1998·147 cites·52 claims
- 1689US5724527AFault-tolerant boot strap mechanism for a multiprocessor systemINTEL CORP·Filed 1995·Granted Mar 3, 1998·160 cites·31 claims
- 1789US5526510AMethod and apparatus for implementing a single clock cycle line replacement in a data cache unitINTEL CORP·Filed 1994·Granted Jun 11, 1996·157 cites·12 claims
- 1888US5881262AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1997·Granted Mar 9, 1999·126 cites·45 claims
- 1988US5778245AMethod and apparatus for dynamic allocation of multiple buffers in a processorINTEL CORP·Filed 1994·Granted Jul 7, 1998·131 cites·22 claims
- 2088US5751983AOut-of-order processor with a memory subsystem which handles speculatively dispatched load operationsFiled 1995·Granted May 12, 1998·140 cites·26 claims
- 2187US8266412B2Hierarchical store buffer having segmented partitionsGLEW ANDREW FORSYTH·Filed 2007·Granted Sep 11, 2012·15 cites·22 claims
- 2286US7644258B2Hybrid branch predictor using component predictors each having confidence and override signalsSEARETE LLC·Filed 2005·Granted Jan 5, 2010·13 cites·10 claims
- 2386US6047369AFlag renaming and flag masks within register alias tableINTEL CORP·Filed 1994·Granted Apr 4, 2000·122 cites·48 claims
- 2485US5627985ASpeculative and committed resource files in an out-of-order processorINTEL CORP·Filed 1994·Granted May 6, 1997·112 cites·33 claims
- 2584US9471373B2Entitlement vector for library usage in managing resource allocation and scheduling based on usage and priorityGERRITY DANIEL A·Filed 2011·Granted Oct 18, 2016·8 cites·39 claims
- 2683US9554487B2Microchannel heat transfer with liquid metalsELWHA LLC·Filed 2012·Granted Jan 24, 2017·4 cites·20 claims
- 2783US5835748AMethod for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register fileINTEL CORP·Filed 1995·Granted Nov 10, 1998·114 cites·157 claims
- 2883US5701508AExecuting different instructions that cause different data type operations to be performed on single logical register fileINTEL CORP·Filed 1995·Granted Dec 23, 1997·94 cites·35 claims
- 2983US5404473AApparatus and method for handling string operations in a pipelined processorINTEL CORP·Filed 1994·Granted Apr 4, 1995·109 cites·37 claims
- 3082US5613083ATranslation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructionsINTEL CORP·Filed 1994·Granted Mar 18, 1997·93 cites·30 claims
- 3182US5517651AMethod and apparatus for loading a segment register in a microprocessor capable of operating in multiple modesINTEL CORP·Filed 1993·Granted May 14, 1996·97 cites·39 claims
- 3281US9298918B2Taint injection and trackingGLEW ANDREW F·Filed 2011·Granted Mar 29, 2016·5 cites·45 claims
- 3381US7149882B2Processor with instructions that operate on different data types stored in the same single logical register fileINTEL CORP·Filed 2004·Granted Dec 12, 2006·23 cites·83 claims
- 3481US6079014AProcessor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural stateINTEL CORP·Filed 1997·Granted Jun 20, 2000·101 cites·23 claims
- 3581US5671444AMethods and apparatus for caching data in a non-blocking manner using a plurality of fill buffersINTEL CORPORAITON·Filed 1996·Granted Sep 23, 1997·104 cites·39 claims
- 3681US5584038AEntry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversedINTEL CORP·Filed 1996·Granted Dec 10, 1996·89 cites·8 claims
- 3781US5446912APartial width stalls within register alias tableINTEL CORP·Filed 1993·Granted Aug 29, 1995·84 cites·34 claims
- 3881US5420991AApparatus and method for maintaining processing consistency in a computer system having multiple processorsINTEL CORP·Filed 1994·Granted May 30, 1995·89 cites·20 claims
- 3980US9558034B2Entitlement vector for managing resource allocationELWHA LLC·Filed 2014·Granted Jan 31, 2017·5 cites·36 claims
- 4080US5724536AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1994·Granted Mar 3, 1998·74 cites·32 claims
- 4180US5630075AWrite combining buffer for sequentially addressed partial line operations originating from a single instructionINTEL CORP·Filed 1995·Granted May 13, 1997·95 cites·34 claims
- 4280US5584001ABranch target buffer for dynamically predicting branch instruction outcomes using a predicted branch historyINTEL CORP·Filed 1995·Granted Dec 10, 1996·95 cites·42 claims
- 4380US5499352AFloating point register alias table FXCH and retirement floating point register arrayINTEL CORP·Filed 1993·Granted Mar 12, 1996·73 cites·51 claims
- 4479US8635415B2Managing and implementing metadata in central processing unit using register extensionsPATEL BAIJU V·Filed 2009·Granted Jan 21, 2014·11 cites·13 claims
- 4579US8275976B2Hierarchical instruction scheduler facilitating instruction replayGLEW ANDREW FORSYTH·Filed 2007·Granted Sep 25, 2012·10 cites·34 claims
- 4679US6035393AStalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolutionINTEL CORP·Filed 1998·Granted Mar 7, 2000·78 cites·21 claims
- 4779US5606670AMethod and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer systemINTEL CORP·Filed 1996·Granted Feb 25, 1997·80 cites·32 claims
- 4878US9813445B2Taint injection and trackingELWHA LLC·Filed 2016·Granted Nov 7, 2017·2 cites·20 claims
- 4978US5687338AMethod and apparatus for maintaining a macro instruction for refetching in a pipelined processorINTEL CORP·Filed 1995·Granted Nov 11, 1997·81 cites·6 claims
- 5077US9703566B2Sharing TLB mappings between contextsCOMBS JONATHAN D·Filed 2011·Granted Jul 11, 2017·5 cites·20 claims
Showing the top 50 of 131 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →