Inventor · disambiguated record
John Pierce
Also filed as: PIERCE JOHN · PIERCE JOHN L · PIERCE JOHN LEROY
14 granted patents·5 pending applications·308 citations·filing 1986–2024
93Inventor score
Files withCADENCE DESIGN SYSTEMS INC5EAGLESTONE PARTNERS I LLC5QUICKET SOLUTIONS INC3EAGLESTONE PARENERS I LLC1MICRO ASI INC1
Top patents by PatentIndex Score
19 records- 0194US6524885B2Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniquesEAGLESTONE PARTNERS I LLC·Filed 2000·Granted Feb 25, 2003·64 cites·11 claims
- 0290US8904321B1System and method for automatically generating coverage constructs and constraint solver distributionsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 2, 2014·19 cites·17 claims
- 0389US4837447ARasterization system for converting polygonal pattern data into a bit-mapRES TRIANGLE INST INC·Filed 1986·Granted Jun 6, 1989·83 cites·56 claims
- 0486US6529022B2Wafer testing interposer for a conventional packageEAGLESTONE PARENERS I LLC·Filed 2000·Granted Mar 4, 2003·50 cites·13 claims
- 0583US6440771B1Method for constructing a wafer interposer by using conductive columnsEAGLESTONE PARTNERS I LLC·Filed 2001·Granted Aug 27, 2002·30 cites·24 claims
- 0679US9477800B1System, method, and computer program product for automatically selecting a constraint solver algorithm in a design verification environmentCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 25, 2016·3 cites·17 claims
- 0779US6673653B2Wafer-interposer using a ceramic substrateEAGLESTONE PARTNERS I LLC·Filed 2001·Granted Jan 6, 2004·29 cites·31 claims
- 0876US9202004B1System, method, and computer program product for ensuring that each simulation in a regression is running a unique configurationCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 1, 2015·4 cites·20 claims
- 0972US9619597B1System, method, and computer program product for electronic design configuration space determination and verificationCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Apr 11, 2017·4 cites·20 claims
- 1072US6933617B2Wafer interposer assemblyEAGLESTONE PARTNERS I LLC·Filed 2003·Granted Aug 23, 2005·13 cites·29 claims
- 1169US9373077B1System and method for identifying constraint solver callsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Jun 21, 2016·6 cites·17 claims
- 1262US2025094168A1Configuration-driven applicationsQUICKET SOLUTIONS INC·Filed 2024·Application pending·0 cites
- 1361US12135966B2Configuration-driven applicationsQUICKET SOLUTIONS INC·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 1449US11842187B2Configuration-driven applicationsQUICKET SOLUTIONS INC·Filed 2021·Granted Dec 12, 2023·0 cites·21 claims
- 1549US7036218B2Method for producing a wafer interposer for use in a wafer interposer assemblyEAGLESTONE PARTNERS I LLC·Filed 2003·Granted May 2, 2006·3 cites·22 claims
- 1634US2002076854A1System, method and apparatus for constructing a semiconductor wafer-interposer using B-Stage laminatesFiled 2000·Application pending·0 cites
- 1734US2002074652A1Method, apparatus and system for multiple chip assembliesFiled 2000·Application pending·0 cites
- 1833US2002075023A1Method for electrically testing a wafer interposerMICRO ASI INC·Filed 2000·Application pending·0 cites
- 1930US2002011859A1Method for forming conductive bumps for the purpose of contrructing a fine pitch test deviceFiled 1998·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →