Inventor · disambiguated record
Doron Orenstien
Also filed as: ORENSTIEN DORON
19 granted patents·1 pending application·630 citations·filing 2000–2013
95Inventor score
Top patents by PatentIndex Score
20 records- 0198US6804632B2Distribution of processing activity across processing hardware based on power consumption considerationsINTEL CORP·Filed 2001·Granted Oct 12, 2004·261 cites·37 claims
- 0296US7043405B2Distribution of processing activity in a multiple core microprocessorINTEL CORP·Filed 2004·Granted May 9, 2006·110 cites·48 claims
- 0395US8504802B2Compressed instruction formatVALENTINE ROBERT·Filed 2012·Granted Aug 6, 2013·20 cites·35 claims
- 0495US6687838B2Low-power processor hint, such as from a PAUSE instructionINTEL CORP·Filed 2000·Granted Feb 3, 2004·105 cites·46 claims
- 0585US7096145B2Deterministic power-estimation for thermal controlINTEL CORP·Filed 2002·Granted Aug 22, 2006·39 cites·19 claims
- 0683US6950903B2Power reduction for processor front-end by caching decoded instructionsINTEL CORP·Filed 2001·Granted Sep 27, 2005·29 cites·12 claims
- 0782US8694758B2Mixing instructions with different register sizesORENSTIEN DORON·Filed 2007·Granted Apr 8, 2014·13 cites·23 claims
- 0879US7130966B2Power reduction for processor front-end by caching decoded instructionsINTEL CORP·Filed 2005·Granted Oct 31, 2006·7 cites·9 claims
- 0977US7613908B2Selective hardware lock disablingINTEL CORP·Filed 2007·Granted Nov 3, 2009·7 cites·12 claims
- 1072US7882325B2Method and apparatus for a double width load using a single width load portINTEL CORP·Filed 2007·Granted Feb 1, 2011·5 cites·14 claims
- 1171US7152167B2Apparatus and method for data bus power controlINTEL CORP·Filed 2002·Granted Dec 19, 2006·16 cites·55 claims
- 1265US10120684B2Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memoryINTEL CORP·Filed 2013·Granted Nov 6, 2018·1 cites·9 claims
- 1365US7653786B2Power reduction for processor front-end by caching decoded instructionsINTEL CORP·Filed 2006·Granted Jan 26, 2010·2 cites·20 claims
- 1458US7159133B2Low-power processor hint, such as from a pause instructionINTEL CORP·Filed 2004·Granted Jan 2, 2007·4 cites·30 claims
- 1555US7114038B2Method and apparatus for communicating between integrated circuits in a low power modeINTEL CORP·Filed 2001·Granted Sep 26, 2006·5 cites·11 claims
- 1652US8909901B2Permute operations with flexible zero controlANDERSON CRISTINA·Filed 2007·Granted Dec 9, 2014·1 cites·21 claims
- 1752US7216240B2Apparatus and method for address bus power controlINTEL CORP·Filed 2002·Granted May 8, 2007·5 cites·30 claims
- 1849US9529592B2Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operationORENSTIEN DORON·Filed 2007·Granted Dec 27, 2016·0 cites·14 claims
- 1946US8386547B2Instruction and logic for performing range detectionINTEL CORP·Filed 2008·Granted Feb 26, 2013·0 cites·23 claims
- 2042US2004128416A1Apparatus and method for address bus power controlFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →