Inventor · disambiguated record
Shailendra Desai
Also filed as: DESAI SHAILENDRA · DESAI SHAILENDRA S
15 granted patents·5 pending applications·151 citations·filing 2000–2022
92Inventor score
Top patents by PatentIndex Score
20 records- 0196US9176913B2Coherence switch for I/O trafficMILLET TIMOTHY J·Filed 2011·Granted Nov 3, 2015·60 cites·20 claims
- 0291US10585825B2Procedures for implementing source based routing within an interconnect fabric on a system on chipPROVINO TECH INC·Filed 2019·Granted Mar 10, 2020·8 cites·22 claims
- 0384US11003604B2Procedures for improving efficiency of an interconnect fabric on a system on chipPROVINO TECH INC·Filed 2019·Granted May 11, 2021·3 cites·27 claims
- 0483US10853282B2Arbitrating portions of transactions over virtual channels associated with an interconnectPROVINO TECH INC·Filed 2019·Granted Dec 1, 2020·3 cites·25 claims
- 0583US10838891B2Arbitrating portions of transactions over virtual channels associated with an interconnectPROVINO TECH INC·Filed 2019·Granted Nov 17, 2020·3 cites·48 claims
- 0681US11640362B2Procedures for improving efficiency of an interconnect fabric on a system on chipGOOGLE LLC·Filed 2021·Granted May 2, 2023·1 cites·20 claims
- 0781US11340671B2Protocol level control for system on a chip (SOC) agent reset and power managementGOOGLE LLC·Filed 2019·Granted May 24, 2022·2 cites·16 claims
- 0881US6957290B1Fast arbitration scheme for a busBROADCOM CORP·Filed 2000·Granted Oct 18, 2005·28 cites·42 claims
- 0976US7320022B2System on a chip for caching of data packets based on a cache miss/hit and a state of a control signalBROADCOM CORP·Filed 2002·Granted Jan 15, 2008·20 cites·10 claims
- 1074US7836220B2Network direct memory accessAPPLE INC·Filed 2006·Granted Nov 16, 2010·5 cites·23 claims
- 1169US11914440B2Protocol level control for system on a chip (SoC) agent reset and power managementGOOGLE LLC·Filed 2022·Granted Feb 27, 2024·0 cites·20 claims
- 1267US8495257B2Network direct memory accessDESAI SHAILENDRA S·Filed 2010·Granted Jul 23, 2013·3 cites·20 claims
- 1366US2022291730A1Protocol Level Control for System on a Chip (SOC) Agent Reset and Power ManagementGOOGLE LLC·Filed 2022·Application pending·0 cites
- 1464US7287649B2System on a chip for packet processingBROADCOM CORP·Filed 2001·Granted Oct 30, 2007·8 cites·13 claims
- 1559US7076586B1Default bus grant to a bus agentBROADCOM CORP·Filed 2000·Granted Jul 11, 2006·7 cites·34 claims
- 1647US2007047572A1Explicit flow control in Gigabit/10 Gigabit Ethernet systemPA SEMI INC·Filed 2005·Application pending·0 cites
- 1747US2005172060A1Fast arbitration scheme for a busFiled 2005·Application pending·0 cites
- 1846US9367474B2Translating cache hintsAPPLE INC·Filed 2013·Granted Jun 14, 2016·0 cites·17 claims
- 1942US2007047443A1Channelized flow controlPA SEMI INC·Filed 2005·Application pending·0 cites
- 2040US2010188980A1Explicit Flow Control in a Gigabit/10 Gigabit Ethernet SystemDESAI SHAILENDRA S·Filed 2010·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Shailendra Desai files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →