Inventor · disambiguated record
Te-Tsung Chao
Also filed as: CHAO TE-TSUNG
7 granted patents·1 pending application·176 citations·filing 2000–2006
87Inventor score
Top patents by PatentIndex Score
8 records- 0186US6291898B1Ball grid array packageADVANCED SEMICONDUCTOR ENG·Filed 2000·Granted Sep 18, 2001·62 cites·9 claims
- 0280US7116002B2Overhang support for a stacked semiconductor device, and method of forming thereofTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 3, 2006·34 cites·6 claims
- 0380US6405357B1Method for positioning bond pads in a semiconductor dieADVANCED SEMICONDUCTOR ENG·Filed 2000·Granted Jun 11, 2002·33 cites·2 claims
- 0467US7588963B2Method of forming overhang support for a stacked semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 15, 2009·4 cites·23 claims
- 0567US6849523B2Process for separating dies on a waferTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Feb 1, 2005·17 cites·8 claims
- 0664US6468813B1Method of automatically identifying and skipping defective work pieces for wire-bonding operationADVANCED SEMICONDUCTOR ENG·Filed 2000·Granted Oct 22, 2002·13 cites·13 claims
- 0764US6391759B1Bonding method which prevents wire sweep and the wire structure thereofADVANCED SEMICONDUCTOR ENG·Filed 2000·Granted May 21, 2002·13 cites·5 claims
- 0837US2006109014A1Test pad and probe card for wafer acceptance testing and other applicationsCHAO TE-TSUNG·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →