Inventor · disambiguated record
Philippe Garnier
Also filed as: GARNIER PHILIPPE
5 granted patents·2 pending applications·1 citations·filing 2004–2019
61Inventor score
Top patents by PatentIndex Score
7 records- 0159US9412589B2Method for fabricating NMOS and PMOS transistors on a substrate of the SOI, in particular FDSOI, type and corresponding integrated circuitST MICROELECTRONICS CROLLES 2 SAS·Filed 2014·Granted Aug 9, 2016·1 cites·20 claims
- 0247US2018286878A1Electronic chip manufacturing methodST MICROELECTRONICS CROLLES 2 SAS·Filed 2018·Application pending·0 cites
- 0346US10014308B2Electronic chip manufacturing methodST MICROELECTRONICS CROLLES 2 SAS·Filed 2016·Granted Jul 3, 2018·0 cites·18 claims
- 0443US8637578B2Reagents and methods for the formation of disulfide bonds and the glycosylation of proteinsDAVIS BENJAMIN GUY·Filed 2004·Granted Jan 28, 2014·0 cites·3 claims
- 0538US11438726B2Method and system for geolocating a terminal in range of a transmitting device of interestSIGFOX·Filed 2019·Granted Sep 6, 2022·0 cites·18 claims
- 0636US2009093126A1Method of and an apparatus for processing a substrateNXP BV·Filed 2006·Application pending·0 cites
- 0733US9437498B2Method for the formation of different gate metal regions of MOS transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2015·Granted Sep 6, 2016·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →