Inventor · disambiguated record
Vladimir Vasekin
Also filed as: VASEKIN VLADIMIR
28 granted patents·4 pending applications·145 citations·filing 2003–2023
95Inventor score
Top patents by PatentIndex Score
32 records- 0192US7707390B2Instruction issue control within a multi-threaded in-order superscalar processorADVANCED RISC MACH LTD·Filed 2007·Granted Apr 27, 2010·29 cites·37 claims
- 0285US7178011B2Predication instruction within a data processing systemADVANCED RISC MACH LTD·Filed 2004·Granted Feb 13, 2007·44 cites·39 claims
- 0383US11416252B2Program instruction fusionADVANCED RISC MACH LTD·Filed 2017·Granted Aug 16, 2022·4 cites·11 claims
- 0478US7529889B2Data processing apparatus and method for performing a cache lookup in an energy efficient mannerADVANCED RISC MACH LTD·Filed 2006·Granted May 5, 2009·9 cites·17 claims
- 0574US7447883B2Allocation of branch target cache resources in dependence upon program instructions within an instruction queueADVANCED RISC MACH LTD·Filed 2006·Granted Nov 4, 2008·7 cites·32 claims
- 0672US7802080B2Null exception handlingADVANCED RISC MACH LTD·Filed 2004·Granted Sep 21, 2010·17 cites·60 claims
- 0767US7877587B2Branch prediction within a multithreaded processorADVANCED RISC MACH LTD·Filed 2006·Granted Jan 25, 2011·6 cites·9 claims
- 0867US7447871B2Data access program instruction encodingADVANCED RISC MACH LTD·Filed 2007·Granted Nov 4, 2008·3 cites·21 claims
- 0965US9645824B2Branch target address cache using hashed fetch addressesADVANCED RISC MACH LTD·Filed 2012·Granted May 9, 2017·2 cites·14 claims
- 1064US7489752B2Synchronisation of signals between asynchronous logicADVANCED RISC MACH LTD·Filed 2005·Granted Feb 10, 2009·3 cites·11 claims
- 1158US7533241B2Variable size cache memory support within an integrated circuitADVANCED RISC MACH LTD·Filed 2006·Granted May 12, 2009·2 cites·16 claims
- 1258US7386709B2Controlling execution of a block of program instructions within a computer processing systemADVANCED RISC MACH LTD·Filed 2004·Granted Jun 10, 2008·5 cites·18 claims
- 1358US7231507B2Data access program instruction encodingADVANCED RISC MACH LTD·Filed 2004·Granted Jun 12, 2007·5 cites·21 claims
- 1456US7111126B2Apparatus and method for loading data valuesADVANCED RISC MACH LTD·Filed 2003·Granted Sep 19, 2006·6 cites·44 claims
- 1555US12292834B2Cache prefetchingADVANCED RISC MACH LTD·Filed 2023·Granted May 6, 2025·0 cites·18 claims
- 1655US8954715B2Thread selection for multithreaded processingVASEKIN VLADIMIR·Filed 2012·Granted Feb 10, 2015·1 cites·18 claims
- 1755US8010774B2Breakpointing on register access events or I/O port access eventsADVANCED RISC MACH LTD·Filed 2006·Granted Aug 30, 2011·2 cites·34 claims
- 1854US11366668B1Method and apparatus for comparing predicated load value with masked load valueADVANCED RISC MACH LTD·Filed 2020·Granted Jun 21, 2022·0 cites·20 claims
- 1950US11947460B2Treating multiple cache lines as a merged cache line to store multiple blocks of dataADVANCED RISC MACH LTD·Filed 2022·Granted Apr 2, 2024·0 cites·19 claims
- 2048US10620962B2Appratus and method for using predicted result valuesADVANCED RISC MACH LTD·Filed 2018·Granted Apr 14, 2020·0 cites·17 claims
- 2147US11409532B1Selecting instructions for a value predictorADVANCED RISC MACH LTD·Filed 2021·Granted Aug 9, 2022·0 cites·14 claims
- 2247US11403105B2Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction predictionADVANCED RISC MACH LTD·Filed 2021·Granted Aug 2, 2022·0 cites·19 claims
- 2347US10719329B2Apparatus and method for using predicted result valuesADVANCED RISC MACH LTD·Filed 2018·Granted Jul 21, 2020·0 cites·20 claims
- 2447US7360061B2Program instruction decompression and compression techniquesADVANCED RISC MACH LTD·Filed 2004·Granted Apr 15, 2008·0 cites·18 claims
- 2546US2005257037A1Controlling execution of a block of program instructions within a computer processing systemADVANCED RISC MACH LTD·Filed 2005·Application pending·0 cites
- 2642US10296349B2Allocating a register to an instruction using register index informationADVANCED RISC MACH LTD·Filed 2016·Granted May 21, 2019·0 cites·18 claims
- 2741US11194577B2Instruction issue according to in-order or out-of-order execution modesADVANCED RISC MACH LTD·Filed 2016·Granted Dec 7, 2021·0 cites·23 claims
- 2841US7900019B2Data access target predictions in a data processing systemADVANCED RISC MACH LTD·Filed 2006·Granted Mar 1, 2011·0 cites·18 claims
- 2938US11429393B2Apparatus and method for supporting out-of-order program execution of instructionsADVANCED RISC MACH LTD·Filed 2015·Granted Aug 30, 2022·0 cites·11 claims
- 3037US2007226471A1Data processing apparatusADVANCED RISC MACH LTD·Filed 2006·Application pending·0 cites
- 3137US2005283593A1Loop end predictionVASEKIN VLADIMIR·Filed 2004·Application pending·0 cites
- 3235US2006271766A1Dynamic fetch rate control of an instruction prefetch unit coupled to a pipelined memory systemADVANCED RISC MACH LTD·Filed 2005·Application pending·0 cites
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