Inventor · disambiguated record
Shaul Yohai Yifrach
Also filed as: YIFRACH SHAUL · Yifrach Shaul Yohai
19 granted patents·11 pending applications·125 citations·filing 2004–2020
91Inventor score
Top patents by PatentIndex Score
30 records- 0188US10157153B2Inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe) systemsQUALCOMM INC·Filed 2016·Granted Dec 18, 2018·9 cites·26 claims
- 0288US7496108B2Method for dynamic management of TCP reassembly buffersIBM·Filed 2004·Granted Feb 24, 2009·80 cites·17 claims
- 0386US10963035B2Low power PCIeQUALCOMM INC·Filed 2018·Granted Mar 30, 2021·4 cites·13 claims
- 0485US10645200B2Alternate acknowledgment (ACK) signals in a coalescing transmission control protocol/internet protocol (TCP/IP) systemQUALCOMM INC·Filed 2017·Granted May 5, 2020·5 cites·15 claims
- 0582US7562168B1Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the sameIBM·Filed 2008·Granted Jul 14, 2009·15 cites·1 claims
- 0667US10042777B2Hardware-based translation lookaside buffer (TLB) invalidationQUALCOMM INC·Filed 2016·Granted Aug 7, 2018·1 cites·20 claims
- 0767US7734854B2Device, system, and method of handling transactionsIBM·Filed 2008·Granted Jun 8, 2010·4 cites·12 claims
- 0864US11287842B2Time synchronization for clocks separated by a communication linkQUALCOMM INC·Filed 2020·Granted Mar 29, 2022·0 cites·19 claims
- 0964US7904865B2Placement driven routingIBM·Filed 2008·Granted Mar 8, 2011·5 cites·6 claims
- 1060US7500062B2Fast path memory read request processing in a multi-level memory architectureIBM·Filed 2005·Granted Mar 3, 2009·2 cites·7 claims
- 1158US10795400B2Time synchronization for clocks separated by a communication linkQUALCOMM INC·Filed 2018·Granted Oct 6, 2020·0 cites·19 claims
- 1255US2020192838A1Extended message signaled interrupts (msi) message dataQUALCOMM INC·Filed 2020·Application pending·0 cites
- 1352US10922252B2Extended message signaled interrupts (MSI) message dataQUALCOMM INC·Filed 2016·Granted Feb 16, 2021·0 cites·31 claims
- 1451US11347667B2Bus controller and related methodsQUALCOMM INC·Filed 2019·Granted May 31, 2022·0 cites·30 claims
- 1550US12218840B2Flexible scheme for adding rules to a NIC pipelineINTEL CORP·Filed 2020·Granted Feb 4, 2025·0 cites·20 claims
- 1648US10310585B2Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systemsQUALCOMM INC·Filed 2017·Granted Jun 4, 2019·0 cites·19 claims
- 1746US10089275B2Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) systemQUALCOMM INC·Filed 2016·Granted Oct 2, 2018·0 cites·30 claims
- 1846US2008247316A1Method Circuit and System for Data Flow ControlBAR-JOSHUA MICHAEL·Filed 2007·Application pending·0 cites
- 1945US2009187683A1Adaptive link width controlIBM·Filed 2008·Application pending·0 cites
- 2045US2019250876A1Split read transactions over an audio communication busQUALCOMM INC·Filed 2019·Application pending·0 cites
- 2144US7747803B2Device, system, and method of handling delayed transactionsIBM·Filed 2007·Granted Jun 29, 2010·0 cites·3 claims
- 2244US2020153593A1Reducing latency on long distance point-to-point linksQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2343US2009185487A1Automated advance link activationIBM·Filed 2008·Application pending·0 cites
- 2441US2006056435A1Method of offloading iSCSI TCP/IP processing from a host processing unit, and related iSCSI TCP/IP offload engineIBM·Filed 2005·Application pending·0 cites
- 2539US9998573B2Hardware-based packet processing circuitryQUALCOMM INC·Filed 2016·Granted Jun 12, 2018·0 cites·30 claims
- 2637US2016371222A1COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYERQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2735US2018041431A1Virtualized internet protocol (ip) packet processing systemQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2835US2012124291A1Secondary Cache Memory With A Counter For Determining Whether to Replace Cached DataACHILLES HEATHER D·Filed 2010·Application pending·0 cites
- 2934US2016337257A1Head-of-line blocking (holb) mitigation in communication devicesQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3032US8949530B2Dynamic index selection in a hardware cacheKRISHNA MVV A·Filed 2011·Granted Feb 3, 2015·0 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →