Inventor · disambiguated record
James D. Warnock
Also filed as: WARNOCK JAMES · WARNOCK JAMES D · WARNOCK JAMES DOUGLAS
66 granted patents·8 pending applications·338 citations·filing 1992–2019
98Inventor score
Top patents by PatentIndex Score
74 records- 0191US6901546B2Enhanced debug scheme for LBISTIBM·Filed 2001·Granted May 31, 2005·56 cites·18 claims
- 0290US7084462B1Parallel field effect transistor structure having a body contactIBM·Filed 2005·Granted Aug 1, 2006·19 cites·18 claims
- 0387US7372305B1Scannable dynamic logic latch circuitIBM·Filed 2006·Granted May 13, 2008·15 cites·20 claims
- 0486US9543935B1Programmable delay circuit including hybrid fin field effect transistors (finFETs)IBM·Filed 2015·Granted Jan 10, 2017·5 cites·9 claims
- 0585US9496447B2Signal distribution in integrated circuit using optical through silicon viaIBM·Filed 2015·Granted Nov 15, 2016·4 cites·11 claims
- 0685US7888959B2Apparatus and method for hardening latches in SOI CMOS devicesIBM·Filed 2007·Granted Feb 15, 2011·11 cites·4 claims
- 0783US8914765B2Power grid generation through modification of an initial power grid based on power grid analysisIBM·Filed 2013·Granted Dec 16, 2014·7 cites·14 claims
- 0882US9618580B2Debugging scan latch circuits using flip devicesIBM·Filed 2015·Granted Apr 11, 2017·2 cites·2 claims
- 0980US10191108B2On-chip sensor for monitoring active circuits on integrated circuit (IC) chipsGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 29, 2019·2 cites·20 claims
- 1080US8104014B2Regular local clock buffer placement and latch clustering by iterative optimizationPURI RUCHIR·Filed 2008·Granted Jan 24, 2012·14 cites·20 claims
- 1177US10678981B2Priority based circuit synthesisIBM·Filed 2018·Granted Jun 9, 2020·2 cites·18 claims
- 1277US10565336B2Pessimism reduction in cross-talk noise determination used in integrated circuit designIBM·Filed 2018·Granted Feb 18, 2020·3 cites·12 claims
- 1376US8589842B1Device-based random variability modeling in timing analysisIBM·Filed 2012·Granted Nov 19, 2013·4 cites·20 claims
- 1475US10288678B2Debugging scan latch circuits using flip devicesIBM·Filed 2017·Granted May 14, 2019·1 cites·2 claims
- 1575US10216885B2Adjusting scan connections based on scan control locationsIBM·Filed 2017·Granted Feb 26, 2019·1 cites·17 claims
- 1675US9910954B2Programmable clock division methodology with in-context frequency checkingIBM·Filed 2016·Granted Mar 6, 2018·2 cites·17 claims
- 1774US7719315B2Programmable local clock bufferIBM·Filed 2006·Granted May 18, 2010·7 cites·21 claims
- 1874US5543731ADynamic and preset static multiplexer in front of latch circuit for use in static circuitsIBM·Filed 1995·Granted Aug 6, 1996·27 cites·5 claims
- 1972US9088279B2Margin improvement for configurable local clock bufferIBM·Filed 2013·Granted Jul 21, 2015·3 cites·17 claims
- 2071US7178075B2High-speed level sensitive scan design test scheme with pipelined test clocksIBM·Filed 2005·Granted Feb 13, 2007·6 cites·17 claims
- 2170US6825695B1Unified local clock buffer structuresIBM·Filed 2003·Granted Nov 30, 2004·14 cites·24 claims
- 2269US6822500B1Methods and apparatus for operating master-slave latchesIBM·Filed 2003·Granted Nov 23, 2004·13 cites·19 claims
- 2369US6744282B1Latching dynamic logic structure, and integrated circuit including sameIBM·Filed 2003·Granted Jun 1, 2004·13 cites·20 claims
- 2469US6718523B2Reduced pessimism clock gating tests for a timing analysis toolIBM·Filed 2001·Granted Apr 6, 2004·15 cites·34 claims
- 2568US7459950B2Pulsed local clock buffer (LCB) characterization ring oscillatorIBM·Filed 2006·Granted Dec 2, 2008·5 cites·6 claims
- 2668US6922818B2Method of power consumption reduction in clocked circuitsIBM·Filed 2001·Granted Jul 26, 2005·14 cites·27 claims
- 2766US7466165B1Transmission gate multiplexerIBM·Filed 2007·Granted Dec 16, 2008·4 cites·6 claims
- 2865US10002881B2Programmable integrated circuit standard cellIBM·Filed 2017·Granted Jun 19, 2018·1 cites·1 claims
- 2965US9614507B2Programmable delay circuit including hybrid fin field effect transistors (finFETs)IBM·Filed 2015·Granted Apr 4, 2017·1 cites·9 claims
- 3065US9575529B2Voltage droop reduction in a processorIBM·Filed 2015·Granted Feb 21, 2017·1 cites·17 claims
- 3165US7165006B2Scan chain disable function for power savingIBM·Filed 2004·Granted Jan 16, 2007·8 cites·9 claims
- 3264US9552455B2Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specificationsGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·1 cites·15 claims
- 3364US8117579B2LSSD compatibility for GSD unified global clock buffersWARNOCK JAMES DOUGLAS·Filed 2008·Granted Feb 14, 2012·6 cites·13 claims
- 3464US7225419B2Methods for modeling latch transparencyIBM·Filed 2004·Granted May 29, 2007·8 cites·13 claims
- 3561US11112854B2Operating pulsed latches on a variable power supplyIBM·Filed 2019·Granted Sep 7, 2021·0 cites·19 claims
- 3661US6927615B2Low skew, power efficient local clock signal generation systemIBM·Filed 2003·Granted Aug 9, 2005·7 cites·20 claims
- 3760US8875084B1Optimal spare latch selection for metal-only ECOsIBM·Filed 2013·Granted Oct 28, 2014·1 cites·18 claims
- 3860US7191419B2Method of timing model abstraction for circuits containing simultaneously switching internal signalsIBM·Filed 2004·Granted Mar 13, 2007·7 cites·17 claims
- 3959US5264387AMethod of forming uniformly thin, isolated silicon mesas on an insulating substrateIBM·Filed 1992·Granted Nov 23, 1993·27 cites·12 claims
- 4057US9891276B2Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution networkIBM·Filed 2015·Granted Feb 13, 2018·0 cites·11 claims
- 4156US10652006B2Determining clock signal quality using a plurality of sensorsIBM·Filed 2017·Granted May 12, 2020·0 cites·15 claims
- 4256US10354046B2Programmable clock division methodology with in-context frequency checkingIBM·Filed 2017·Granted Jul 16, 2019·0 cites·11 claims
- 4356US9543463B2Signal distribution in integrated circuit using optical through silicon viaIBM·Filed 2014·Granted Jan 10, 2017·0 cites·11 claims
- 4455US10386912B2Operating pulsed latches on a variable power supplyIBM·Filed 2017·Granted Aug 20, 2019·0 cites·18 claims
- 4555US9664735B2Debugging scan latch circuits using flip devicesIBM·Filed 2015·Granted May 30, 2017·0 cites·9 claims
- 4653US10666415B2Determining clock signal quality using a plurality of sensorsIBM·Filed 2017·Granted May 26, 2020·0 cites·9 claims
- 4753US9985616B2Programmable delay circuit including hybrid fin field effect transistors (finFETs)IBM·Filed 2017·Granted May 29, 2018·0 cites·7 claims
- 4853US9762212B1Initializing scannable and non-scannable latches from a common clock bufferIBM·Filed 2016·Granted Sep 12, 2017·0 cites·13 claims
- 4952US2014141607A1Continuous via for power gridIBM·Filed 2013·Application pending·0 cites
- 5051US9934348B2Adjusting scan connections based on scan control locationsIBM·Filed 2015·Granted Apr 3, 2018·0 cites·20 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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