Inventor · disambiguated record
Kazunori Hayata
Also filed as: HAYATA KAZUNORI
8 granted patents·4 pending applications·29 citations·filing 2010–2023
79Inventor score
Top patents by PatentIndex Score
12 records- 0190US8815648B1Multi-step sintering of metal paste for semiconductor device wire bondingTEXAS INSTRUMENTS INC·Filed 2013·Granted Aug 26, 2014·25 cites·14 claims
- 0270US8716068B2Method for contacting agglomerate terminals of semiconductor packagesTEXAS INSTRUMENTS INC·Filed 2013·Granted May 6, 2014·2 cites·17 claims
- 0360US12133049B2Reduced light reflection packageINVENSENSE INC·Filed 2023·Granted Oct 29, 2024·0 cites·19 claims
- 0456US8643165B2Semiconductor device having agglomerate terminalsEDWARDS DARVIN R·Filed 2012·Granted Feb 4, 2014·1 cites·2 claims
- 0555US11800297B2Reduced light reflection packageINVENSENSE INC·Filed 2021·Granted Oct 24, 2023·0 cites·28 claims
- 0653US9536753B2Circuit substrate interconnectTEXAS INSTRUMENTS INC·Filed 2014·Granted Jan 3, 2017·1 cites·13 claims
- 0751US11760627B2MEMS stress reduction structure embedded into packageINVENSENSE INC·Filed 2021·Granted Sep 19, 2023·0 cites·29 claims
- 0850US11012790B2Flipchip packageINVENSENSE INC·Filed 2019·Granted May 18, 2021·0 cites·20 claims
- 0940US2014284779A1Semiconductor device having reinforced wire bonds to metal terminalsTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
- 1036US2010255641A1Semiconductor Manufacturing MethodTEXAS INSTRUMENTS INC·Filed 2010·Application pending·0 cites
- 1136US2015340324A1Integrated Circuit Die And PackageTEXAS INSTRUMENTS INC·Filed 2014·Application pending·0 cites
- 1236US2014091465A1Leadframe having sloped metal terminals for wirebondingTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →