Inventor · disambiguated record
Gulzar Kathawala
Also filed as: KATHAWALA GULZAR · KATHAWALA GULZAR A · KATHAWALA GULZAR AHMED
14 granted patents·3 pending applications·54 citations·filing 2007–2024
90Inventor score
Files withSPANSION LLC6SANDISK TECHNOLOGIES LLC3SK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM2WESTERN DIGITAL TECH INC2KATHAWALA GULZAR A1
Top patents by PatentIndex Score
17 records- 0192US10014056B1Changing storage parametersSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Jul 3, 2018·14 cites·20 claims
- 0290US10032488B1System and method of managing data in a non-volatile memory having a staging sub-driveSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jul 24, 2018·7 cites·21 claims
- 0386US10338841B2Block management for data streamsWESTERN DIGITAL TECH INC·Filed 2017·Granted Jul 2, 2019·4 cites·24 claims
- 0484US10552259B2Recovery combining hard decoding, soft decoding and artificial codeword generationWESTERN DIGITAL TECH INC·Filed 2018·Granted Feb 4, 2020·8 cites·29 claims
- 0569US12511193B1Methods and systems for SLC copyback operationsSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2024·Granted Dec 30, 2025·0 cites·20 claims
- 0665US7952938B2Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memorySPANSION LLC·Filed 2010·Granted May 31, 2011·3 cites·20 claims
- 0761US10108470B2Parity storage managementSANDISK TECHNOLOGIES INC·Filed 2015·Granted Oct 23, 2018·2 cites·20 claims
- 0861US9111985B1Shallow bipolar junction transistorROY ALOK NANDINI·Filed 2007·Granted Aug 18, 2015·4 cites·7 claims
- 0959US7944746B2Room temperature drift suppression via soft program after eraseSPANSION LLC·Filed 2007·Granted May 17, 2011·6 cites·25 claims
- 1056US7626869B2Multi-phase wordline erasing for flash memorySPANSION LLC·Filed 2007·Granted Dec 1, 2009·3 cites·20 claims
- 1153US2025036289A1Progressive redundant array of inexpensive disks (raid) for memory devicesSK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM·Filed 2023·Application pending·0 cites
- 1251US7995386B2Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturbSPANSION LLC·Filed 2008·Granted Aug 9, 2011·2 cites·20 claims
- 1350US8995198B1Multi-pass soft programmingSPANSION LLC·Filed 2013·Granted Mar 31, 2015·1 cites·20 claims
- 1444US2025246248A1Pattern analysis enabled read operation in nand componentSK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM·Filed 2023·Application pending·0 cites
- 1543US9153596B2Adjacent wordline disturb reduction using boron/indium implantKATHAWALA GULZAR A·Filed 2009·Granted Oct 6, 2015·0 cites·20 claims
- 1638US2017148525A1Method and System For Adaptively Adjusting a Verify Voltage to Reduce Storage Raw Bit Error RateSANDISK TECHNOLOGIES LLC·Filed 2016·Application pending·0 cites
- 1736US9142311B2Screening for reference cells in a memorySPANSION LLC·Filed 2013·Granted Sep 22, 2015·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →