Inventor · disambiguated record
Ketan Padalia
Also filed as: PADALIA KETAN
22 granted patents·3 pending applications·232 citations·filing 2002–2020
95Inventor score
Top patents by PatentIndex Score
25 records- 0195US9569574B1Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2014·Granted Feb 14, 2017·35 cites·19 claims
- 0294US8281274B1Method and apparatus for performing efficient incremental compilationPADALIA KETAN·Filed 2010·Granted Oct 2, 2012·23 cites·40 claims
- 0389US8539418B1Method and apparatus for performing efficient incremental compilationPADALIA KETAN·Filed 2012·Granted Sep 17, 2013·10 cites·24 claims
- 0487US11093672B2Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2020·Granted Aug 17, 2021·2 cites·19 claims
- 0587US7558812B1Structures for LUT-based arithmetic in PLDsALTERA CORP·Filed 2003·Granted Jul 7, 2009·25 cites·12 claims
- 0686US7681165B2Apparatus and methods for congestion estimation and optimization for computer-aided design softwareALTERA CORP·Filed 2006·Granted Mar 16, 2010·21 cites·35 claims
- 0786US6871328B1Method for mapping logic design memory into physical memory device of a programmable logic deviceALTERA CORP·Filed 2002·Granted Mar 22, 2005·39 cites·77 claims
- 0885US7268584B1Adder circuitry for a programmable logic deviceALTERA CORP·Filed 2005·Granted Sep 11, 2007·15 cites·27 claims
- 0983US8504970B1Method and apparatus for performing automated timing closure analysis for systems implemented on target devicesMALHOTRA SHAWN·Filed 2011·Granted Aug 6, 2013·11 cites·26 claims
- 1083US7370291B2Method for mapping logic design memory into physical memory devices of a programmable logic deviceALTERA CORP·Filed 2005·Granted May 6, 2008·11 cites·66 claims
- 1180US7493585B1Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocksALTERA CORP·Filed 2006·Granted Feb 17, 2009·11 cites·31 claims
- 1275US9594859B1Apparatus and associated methods for parallelizing clustering and placementPADALIA KETAN·Filed 2008·Granted Mar 14, 2017·8 cites·33 claims
- 1373US9658830B1Structures for LUT-based arithmetic in PLDsALTERA CORP·Filed 2014·Granted May 23, 2017·2 cites·23 claims
- 1471US10635772B1Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2016·Granted Apr 28, 2020·1 cites·8 claims
- 1569US7707532B1Techniques for grouping circuit elements into logic blocksALTERA CORP·Filed 2007·Granted Apr 27, 2010·4 cites·21 claims
- 1668US8856713B1Method and apparatus for performing efficient incremental compilationALTERA CORP·Filed 2013·Granted Oct 7, 2014·1 cites·28 claims
- 1765US7441208B1Methods for designing integrated circuitsALTERA CORP·Filed 2005·Granted Oct 21, 2008·3 cites·18 claims
- 1865US7415682B2Automatic adjustment of optimization effort in configuring programmable devicesALTERA CORP·Filed 2005·Granted Aug 19, 2008·3 cites·28 claims
- 1960US10073941B1Method and apparatus for performing efficient incremental compilationALTERA CORP·Filed 2014·Granted Sep 11, 2018·0 cites·22 claims
- 2059US8499273B1Systems and methods for optimizing placement and routingBOZMAN KIMBERLEY ANNE·Filed 2010·Granted Jul 30, 2013·2 cites·21 claims
- 2158US8788550B1Structures for LUT-based arithmetic in PLDsPADALIA KETAN·Filed 2009·Granted Jul 22, 2014·2 cites·20 claims
- 2258US2017322775A1Structures for lut-based arithmetic in pldsALTERA CORP·Filed 2017·Application pending·0 cites
- 2353US7275228B1Techniques for grouping circuit elements into logic blocksALTERA CORP·Filed 2003·Granted Sep 25, 2007·3 cites·27 claims
- 2447US2010070979A1Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design SoftwareLUDWIN ADRIAN·Filed 2009·Application pending·0 cites
- 2542US2007192766A1Apparatus and methods for parallelizing integrated circuit computer-aided design softwarePADALIA KETAN·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →