Inventor · disambiguated record
Nathan Francis Sheeley
Also filed as: SHEELEY NATHAN · SHEELEY NATHAN FRANCIS
8 granted patents·3 pending applications·63 citations·filing 2005–2024
84Inventor score
Top patents by PatentIndex Score
11 records- 0195US11366783B1Multi-headed multi-buffer for buffering data for processingSAMBANOVA SYSTEMS INC·Filed 2021·Granted Jun 21, 2022·6 cites·24 claims
- 0295US11204889B1Tensor partitioning and partition access orderSAMBANOVA SYSTEMS INC·Filed 2021·Granted Dec 21, 2021·10 cites·20 claims
- 0394US11443014B1Sparse matrix multiplier in hardware and a reconfigurable data processor including sameSAMBANOVA SYSTEMS INC·Filed 2021·Granted Sep 13, 2022·8 cites·30 claims
- 0491US12045591B2Skip buffer splittingSAMBANOVA SYSTEMS INC·Filed 2022·Granted Jul 23, 2024·2 cites·6 claims
- 0590US7965773B1Macroblock cacheADVANCED MICRO DEVICES INC·Filed 2005·Granted Jun 21, 2011·36 cites·19 claims
- 0676US2024370240A1Coarse-grained reconfigurable processor array with optimized buffersSAMBANOVA SYSTEMS INC·Filed 2024·Application pending·0 cites
- 0770US2023409233A1Buffer Fusion and Layout OptimizationSAMBANOVA SYSTEMS INC·Filed 2022·Application pending·0 cites
- 0862US11561925B2Tensor partitioning and partition access orderSAMBANOVA SYSTEMS INC·Filed 2021·Granted Jan 24, 2023·0 cites·20 claims
- 0944US8448107B2Method for piecewise hierarchical sequential verificationSHEELEY NATHAN FRANCIS·Filed 2009·Granted May 21, 2013·1 cites·20 claims
- 1043US10740102B2Hardware mechanism to mitigate stalling of a processor coreORACLE INT CORP·Filed 2017·Granted Aug 11, 2020·0 cites·20 claims
- 1136US2007129923A1Dynamic synchronizer simulationADVANCED MICRO DEVICES INC·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →