Inventor · disambiguated record
Nurwati Devnani
Also filed as: DEVNANI NURWATI S · DEVNANI NURWATI SUWENDI
8 granted patents·3 pending applications·91 citations·filing 2002–2013
86Inventor score
Files withAGILENT TECHNOLOGIES INC4AVAGO TECH ECBU IP SG PTE LTD1AVAGO TECHNOLOGIES ENTPR IP SI1AVAGO TECHNOLOGIES GENERAL IP1GALLEGOS ADAM1
Top patents by PatentIndex Score
11 records- 0190US7609125B2System, device and method for reducing cross-talk in differential signal conductor pairsAVAGO TECHNOLOGIES ENTPR IP SI·Filed 2006·Granted Oct 27, 2009·36 cites·28 claims
- 0276US6960917B2Methods and apparatus for diagnosing defect locations in electrical paths of connectors of circuit assembliesAGILENT TECHNOLOGIES INC·Filed 2003·Granted Nov 1, 2005·20 cites·24 claims
- 0367US9041208B2Laminate interconnect having a coaxial via structureGALLEGOS ADAM·Filed 2011·Granted May 26, 2015·4 cites·20 claims
- 0465US9166550B2System and method for using a reference plane to control transmission line characteristic impedanceAVAGO TECHNOLOGIES GENERAL IP·Filed 2013·Granted Oct 20, 2015·2 cites·16 claims
- 0562US7227254B2Integrated circuit packageAGILENT TECHNOLOGIES INC·Filed 2002·Granted Jun 5, 2007·9 cites·19 claims
- 0662US7001834B2Integrated circuit and method of manufacturing an integrated circuit and packageAGILENT TECHNOLOGIES INC·Filed 2003·Granted Feb 21, 2006·9 cites·9 claims
- 0757US6630628B2High-performance laminate for integrated circuit interconnectionAGILENT TECHNOLOGIES INC·Filed 2002·Granted Oct 7, 2003·9 cites·21 claims
- 0855US7855614B2Integrated circuit transmission lines, methods for designing integrated circuits using the same and methods to improve return lossAVAGO TECH ECBU IP SG PTE LTD·Filed 2008·Granted Dec 21, 2010·2 cites·13 claims
- 0939US2005121766A1Integrated circuit and method of manufacturing an integrated circuit and packageFiled 2005·Application pending·0 cites
- 1035US2005253616A1Method and apparatus for testing and diagnosing electrical paths through area array integrated circuitsPARKER KENNETH P·Filed 2004·Application pending·0 cites
- 1133US2008237893A1Anti Pad To Reduce Parasitic Capacitance And Improve Return Loss In A Semiconductor Die And PackageQUACH MINH VAN·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →