Inventor · disambiguated record
Cédric Marchand
Also filed as: MARCHAND CÉDRIC
9 granted patents·6 citations·filing 2017–2019
77Inventor score
Files withUNIV BRETAGNE SUD9
Top patents by PatentIndex Score
9 records- 0176US10560120B2Elementary check node processing for syndrome computation for non-binary LDPC codes decodingUNIV BRETAGNE SUD·Filed 2017·Granted Feb 11, 2020·3 cites·15 claims
- 0267US11133827B2Simplified, presorted, syndrome-based, extended min-sum (EMS) decoding of non-binary LDPC codesUNIV BRETAGNE SUD·Filed 2018·Granted Sep 28, 2021·2 cites·14 claims
- 0358US10476523B2Elementary check node-based syndrome decoding using pre-sorted inputsUNIV BRETAGNE SUD·Filed 2017·Granted Nov 12, 2019·1 cites·25 claims
- 0440US11290128B2Simplified check node processing in non-binary LDPC decoderUNIV BRETAGNE SUD·Filed 2018·Granted Mar 29, 2022·0 cites·16 claims
- 0538US11095308B2Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codesUNIV BRETAGNE SUD·Filed 2018·Granted Aug 17, 2021·0 cites·16 claims
- 0637US11476870B2Variable node processing methods and devices for message-passing decoding of non-binary codesUNIV BRETAGNE SUD·Filed 2019·Granted Oct 18, 2022·0 cites·14 claims
- 0736US11545998B2Offset value determination in a check node processing unit for message-passing decoding of non-binary codesUNIV BRETAGNE SUD·Filed 2019·Granted Jan 3, 2023·0 cites·10 claims
- 0835US11245421B2Check node processing methods and devices with insertion sortUNIV BRETAGNE SUD·Filed 2019·Granted Feb 8, 2022·0 cites·10 claims
- 0933US10637510B2Methods and devices for error correcting codes decodingUNIV BRETAGNE SUD·Filed 2017·Granted Apr 28, 2020·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →