Inventor · disambiguated record
David Scott Ray
Also filed as: RAY DAVID · RAY DAVID S · RAY DAVID SCOTT
32 granted patents·5 pending applications·825 citations·filing 1989–2024
97Inventor score
Files withIBM24QUALCOMM INC3ALTRIA CLIENT SERVICES LLC2PHILIP MORRIS USA INC2ABERNATHY CHRISTOPHER MICHAEL1
Top patents by PatentIndex Score
37 records- 0195US6574712B1Software prefetch system and method for predetermining amount of streamed dataIBM·Filed 2000·Granted Jun 3, 2003·130 cites·16 claims
- 0286US7302527B2Systems and methods for executing load instructions that avoid order violationsIBM·Filed 2004·Granted Nov 27, 2007·47 cites·32 claims
- 0385US9389867B2Speculative finish of instruction execution in a processor coreIBM·Filed 2015·Granted Jul 12, 2016·4 cites·6 claims
- 0483US6915415B2Method and apparatus for mapping software prefetch instructions to hardware prefetch logicIBM·Filed 2002·Granted Jul 5, 2005·37 cites·25 claims
- 0583US6460115B1System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanismIBM·Filed 1999·Granted Oct 1, 2002·109 cites·15 claims
- 0681US8156287B2Adaptive data prefetchBOSE PRADIP·Filed 2009·Granted Apr 10, 2012·11 cites·16 claims
- 0779US9384002B2Speculative finish of instruction execution in a processor coreIBM·Filed 2012·Granted Jul 5, 2016·4 cites·8 claims
- 0878US11550723B2Method, apparatus, and system for memory bandwidth aware data prefetchingQUALCOMM INC·Filed 2018·Granted Jan 10, 2023·2 cites·26 claims
- 0978US6957305B2Data streaming mechanism in a microprocessorIBM·Filed 2002·Granted Oct 18, 2005·24 cites·7 claims
- 1078US6446167B1Cache prefetching of L2 and L3IBM·Filed 1999·Granted Sep 3, 2002·79 cites·18 claims
- 1178US2025104121A1Mobile tobacco receiving stationALTRIA CLIENT SERVICES LLC·Filed 2024·Application pending·0 cites
- 1274US8082423B2Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updatesABERNATHY CHRISTOPHER MICHAEL·Filed 2005·Granted Dec 20, 2011·7 cites·1 claims
- 1373US8086801B2Loading data to vector renamed register from across multiple cache linesHRUSECKY DAVID A·Filed 2009·Granted Dec 27, 2011·8 cites·20 claims
- 1473US6085291ASystem and method for selectively controlling fetching and prefetching of data to a processorIBM·Filed 1995·Granted Jul 4, 2000·67 cites·20 claims
- 1572US7464242B2Method of load/store dependencies detection with dynamically changing address lengthIBM·Filed 2005·Granted Dec 9, 2008·6 cites·14 claims
- 1667US6535962B1System and method for prefetching data using a hardware prefetch mechanismIBM·Filed 1999·Granted Mar 18, 2003·48 cites·20 claims
- 1767US5075840ATightly coupled multiprocessor instruction synchronizationIBM·Filed 1989·Granted Dec 24, 1991·36 cites·6 claims
- 1864US7376816B2Method and systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2004·Granted May 20, 2008·8 cites·7 claims
- 1963US7769985B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2008·Granted Aug 3, 2010·2 cites·9 claims
- 2063US7730290B2Systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2008·Granted Jun 1, 2010·2 cites·13 claims
- 2161US12175509B2Mobile tobacco receiving stationALTRIA CLIENT SERVICES LLC·Filed 2020·Granted Dec 24, 2024·0 cites·20 claims
- 2261US6112297AApparatus and method for processing misaligned load instructions in a processor supporting out of order executionIBM·Filed 1998·Granted Aug 29, 2000·39 cites·9 claims
- 2361US5613080AMultiple execution unit dispatch with instruction shifting between first and second instruction buffers based upon data dependencyIBM·Filed 1996·Granted Mar 18, 1997·39 cites·20 claims
- 2459US6148394AApparatus and method for tracking out of order load instructions to avoid data coherency violations in a processorIBM·Filed 1998·Granted Nov 14, 2000·37 cites·7 claims
- 2557US10664275B2Speeding up younger store instruction execution after a sync instructionIBM·Filed 2018·Granted May 26, 2020·0 cites·21 claims
- 2657US7953960B2Method and apparatus for delaying a load miss flush until issuing the dependent instructionIBM·Filed 2005·Granted May 31, 2011·1 cites·21 claims
- 2757US2009234709A1Mobile tobacco receiving stationPHILIP MORRIS USA INC·Filed 2008·Application pending·0 cites
- 2856US6463514B1Method to arbitrate for a cache blockIBM·Filed 1998·Granted Oct 8, 2002·30 cites·17 claims
- 2956US2025207111A1Mobile genetic elements from eptesicus fuscusSALIOGEN THERAPEUTICS INC·Filed 2023·Application pending·0 cites
- 3051US11061822B2Method, apparatus, and system for reducing pipeline stalls due to address translation missesQUALCOMM INC·Filed 2018·Granted Jul 13, 2021·0 cites·24 claims
- 3151US6035394ASystem for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallelIBM·Filed 1998·Granted Mar 7, 2000·25 cites·20 claims
- 3251US5440703ASystem and method for saving state information in a multi-execution unit processor when interruptable instructions are identifiedIBM·Filed 1993·Granted Aug 8, 1995·22 cites·23 claims
- 3348US10572920B2Mobile tobacco receiving stationPHILIP MORRIS USA INC·Filed 2014·Granted Feb 25, 2020·0 cites·10 claims
- 3447US7363468B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2004·Granted Apr 22, 2008·1 cites·5 claims
- 3544US10067765B2Speeding up younger store instruction execution after a sync instructionEISEN SUSAN E·Filed 2012·Granted Sep 4, 2018·0 cites·20 claims
- 3643US2019370176A1Adaptively predicting usefulness of prefetches generated by hardware prefetch engines in processor-based devicesQUALCOMM INC·Filed 2018·Application pending·0 cites
- 3743US2006224864A1System and method for handling multi-cycle non-pipelined instruction sequencingDEMENT JONATHAN J·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →