Inventor · disambiguated record
Jakob Raymond Jones
Also filed as: JONES JAKOB · JONES JAKOB RAYMOND
17 granted patents·1 pending application·46 citations·filing 2012–2024
91Inventor score
Top patents by PatentIndex Score
18 records- 0196US10445278B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2016·Granted Oct 15, 2019·13 cites·21 claims
- 0291US9633158B1Selectable reconfiguration for dynamically reconfigurable IP coresALTERA CORP·Filed 2014·Granted Apr 25, 2017·11 cites·21 claims
- 0388US10102172B1Method and apparatus for performing a single pass compilation for systems with dynamically reconfigurable logic blocksALTERA CORP·Filed 2015·Granted Oct 16, 2018·11 cites·18 claims
- 0488US2025021506A1Interface Bridge Between Integrated Circuit DieALTERA CORP·Filed 2024·Application pending·0 cites
- 0584US11100029B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2019·Granted Aug 24, 2021·2 cites·24 claims
- 0683US12135667B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 0777US11693810B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2021·Granted Jul 4, 2023·0 cites·20 claims
- 0873US11237998B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2020·Granted Feb 1, 2022·0 cites·54 claims
- 0972US12191893B2Seemingly monolithic interface between separate integrated circuit dieINTEL CORP·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 1070US9225344B2Methods and apparatus for aligning clock signals on an integrated circuitALTERA CORP·Filed 2013·Granted Dec 29, 2015·3 cites·18 claims
- 1167US9628095B1Parameterizable method for simulating PLL behaviorLiveris Nikolaos·Filed 2012·Granted Apr 18, 2017·5 cites·28 claims
- 1262US9311106B1Multiple reconfiguration profiles for dynamically reconfigurable intellectual property coresALTERA CORP·Filed 2013·Granted Apr 12, 2016·1 cites·17 claims
- 1361US11075648B2Seemingly monolithic interface between separate integrated circuit dieINTEL CORP·Filed 2019·Granted Jul 27, 2021·0 cites·20 claims
- 1459US10831960B1Selectable reconfiguration for dynamically reconfigurable IP coresALTERA CORP·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 1555US10439639B2Seemingly monolithic interface between separate integrated circuit dieINTEL CORP·Filed 2016·Granted Oct 8, 2019·0 cites·21 claims
- 1654US10127341B1Selectable reconfiguration for dynamically reconfigurable IP coresALTERA CORP·Filed 2017·Granted Nov 13, 2018·0 cites·9 claims
- 1751US12038837B2Chiplet architecture data processing devices and methodsGOOGLE LLC·Filed 2022·Granted Jul 16, 2024·0 cites·20 claims
- 1846US10242141B2Reset sequencing for reducing noise on a power distribution networkALTERA CORP·Filed 2016·Granted Mar 26, 2019·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →