Inventor · disambiguated record
Patrick Van De Steeg
Also filed as: VAN DE STEEG PATRICK
9 granted patents·39 citations·filing 2003–2019
84Inventor score
Top patents by PatentIndex Score
9 records- 0185US9691496B1High density ROM cell with dual bit storage for high speed and low voltageNXP BV·Filed 2016·Granted Jun 27, 2017·10 cites·18 claims
- 0284US10685703B2Transistor body bias control circuit for SRAM cellsNXP BV·Filed 2018·Granted Jun 16, 2020·8 cites·16 claims
- 0382US9202588B11T compact ROM cell with dual bit storage for high speed and low voltageNXP BV·Filed 2014·Granted Dec 1, 2015·9 cites·20 claims
- 0476US9406374B1Mitigating leakage in memory circuitsNXP BV·Filed 2015·Granted Aug 2, 2016·5 cites·20 claims
- 0566US10679714B2ROM cell with transistor body bias control circuitNXP BV·Filed 2019·Granted Jun 9, 2020·2 cites·19 claims
- 0643US8139401B2Integrated circuit with a memory matrix with a delay monitoring columnVEENDRICK HENDRICUS J M·Filed 2009·Granted Mar 20, 2012·1 cites·10 claims
- 0737US11074946B2Temperature dependent voltage differential sense-amplifierNXP BV·Filed 2019·Granted Jul 27, 2021·0 cites·14 claims
- 0834US7038936B2Reading circuit for reading a memory cellSEEVINCK EVERT·Filed 2003·Granted May 2, 2006·4 cites·6 claims
- 0932US10236071B1Dual-bit ROM cell with virtual ground line and programmable metal trackNXP BV·Filed 2017·Granted Mar 19, 2019·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →