Inventor · disambiguated record
Mark A. Gonzales
Also filed as: GONZALES MARK · GONZALES MARK A
15 granted patents·1 pending application·1,159 citations·filing 1990–2002
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
16 records- 0195US6101614AMethod and apparatus for automatically scrubbing ECC errors in memory via hardwareINTEL CORP·Filed 1997·Granted Aug 8, 2000·279 cites·18 claims
- 0294US5546546AMethod and apparatus for maintaining transaction ordering and arbitrating in a bus bridgeINTEL CORP·Filed 1994·Granted Aug 13, 1996·181 cites·28 claims
- 0386US6021451AMethod and apparatus for maintaining transaction ordering and arbitrating in a bus bridgeINTEL CORP·Filed 1998·Granted Feb 1, 2000·102 cites·32 claims
- 0486US5535340AMethod and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridgeINTEL CORP·Filed 1994·Granted Jul 9, 1996·122 cites·37 claims
- 0585US5191649AMultiprocessor computer system with data bus and ordered and out-of-order split data transactionsINTEL CORP·Filed 1990·Granted Mar 2, 1993·132 cites·5 claims
- 0677US6496822B2Methods of providing computer systems with bundled access to restricted-access databasesMICRON TECHNOLOGY INC·Filed 1999·Granted Dec 17, 2002·80 cites·22 claims
- 0774US6718441B2Method to prefetch data from system memory using a bus interface unitINTEL CORP·Filed 2002·Granted Apr 6, 2004·17 cites·6 claims
- 0872US5835739AMethod and apparatus for maintaining transaction ordering and arbitrating in a bus bridgeINTEL CORP·Filed 1997·Granted Nov 10, 1998·49 cites·28 claims
- 0971US6487626B2Method and apparatus of bus interface for a processorINTEL CORPORAITON·Filed 2001·Granted Nov 26, 2002·17 cites·23 claims
- 1071US5471601AMemory device and method for avoiding live lock of a DRAM with cacheINTEL CORP·Filed 1992·Granted Nov 28, 1995·57 cites·7 claims
- 1168US5261109ADistributed arbitration method and apparatus for a computer bus using arbitration groupsINTEL CORP·Filed 1993·Granted Nov 9, 1993·55 cites·5 claims
- 1257US6453388B1Computer system having a bus interface unit for prefetching data from system memoryINTEL CORP·Filed 1995·Granted Sep 17, 2002·30 cites·22 claims
- 1355US5455939AMethod and apparatus for error detection and correction of data transferred between a CPU and system memoryINTEL CORP·Filed 1994·Granted Oct 3, 1995·29 cites·2 claims
- 1440US2003088567A1Methods of providing computer systems with bundled access to restricted-access databasesROSENFELT MICHAEL·Filed 2002·Application pending·0 cites
- 1534US6412033B1Method and apparatus for data and address transmission over a busINTEL CORP·Filed 1998·Granted Jun 25, 2002·6 cites·54 claims
- 1631US5898894ACPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time intervalINTEL CORP·Filed 1997·Granted Apr 27, 1999·3 cites·2 claims
Join the waitlist — get patent alerts
Get an alert when Mark A. Gonzales files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →