Inventor · disambiguated record
Sachin D. Dasnurkar
Also filed as: DASNURKAR SACHIN · DASNURKAR SACHIN D · DASNURKAR SACHIN DILEEP
7 granted patents·7 pending applications·76 citations·filing 2010–2016
83Inventor score
Top patents by PatentIndex Score
14 records- 0193US8283933B2Systems and methods for built in self test jitter measurementDASNURKAR SACHIN D·Filed 2010·Granted Oct 9, 2012·27 cites·29 claims
- 0292US8310385B2Systems and methods for vector-based analog-to-digital converter sequential testingDASNURKAR SACHIN D·Filed 2010·Granted Nov 13, 2012·26 cites·30 claims
- 0385US8510073B2Real-time adaptive hybrid BiST solution for low-cost and low-resource ate production testing of analog-to-digital convertersDASNURKAR SACHIN D·Filed 2010·Granted Aug 13, 2013·12 cites·24 claims
- 0485US8106801B2Methods and apparatus for built in self test of analog-to-digital convertorsDASNURKAR SACHIN D·Filed 2010·Granted Jan 31, 2012·9 cites·40 claims
- 0564US9557797B2Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and powerQUALCOMM INC·Filed 2014·Granted Jan 31, 2017·1 cites·29 claims
- 0649US10215800B2Device specific thermal mitigationQUALCOMM INC·Filed 2015·Granted Feb 26, 2019·1 cites·16 claims
- 0739US2014225635A1All-digital phase locked loop self test systemQUALCOMM INC·Filed 2013·Application pending·0 cites
- 0836US9179406B2Method and apparatus for enhanced sleep mode tiering to optimize standby time and test yieldQUALCOMM INC·Filed 2012·Granted Nov 3, 2015·0 cites·17 claims
- 0936US2015189602A1Core level optimized low power modeQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1035US2010293426A1Systems and methods for a phase locked loop built in self testQUALCOMM INC·Filed 2010·Application pending·0 cites
- 1135US2015261545A1Core selection schemeQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1233US2015198988A1Core specific process voltage scaling for optimizing multi-core operationQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1332US2015346745A1Thermally-adaptive voltage scaling for supply voltage supervisor power optimizationQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1431US2017242070A1Automatic failure identification and failure pattern identification within an ic waferQUALCOMM INC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →