Inventor · disambiguated record
Daren Eugene Streett
Also filed as: STREETT DAREN · STREETT DAREN E · STREETT DAREN EUGENE
16 granted patents·9 pending applications·23 citations·filing 2006–2023
87Inventor score
Technology areasG06F
Files withMICROSOFT TECHNOLOGY LICENSING LLC13QUALCOMM INC9KOTHARI KULIN N1MORROW MICHAEL WILLIAM1STREETT DAREN EUGENE1
Top patents by PatentIndex Score
25 records- 0182US9477478B2Multi level indirect predictor using confidence counter and program counter address filter schemeKOTHARI KULIN N·Filed 2012·Granted Oct 25, 2016·10 cites·17 claims
- 0271US12229568B2Methods and circuitry for efficient management of local branch history registersMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 0371US7802055B2Virtually-tagged instruction cache with physically-tagged behaviorQUALCOMM INC·Filed 2006·Granted Sep 21, 2010·5 cites·22 claims
- 0467US11768688B1Methods and circuitry for efficient management of local branch history registersMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 26, 2023·0 cites·20 claims
- 0565US8352713B2Debug circuit comparing processor instruction set operating modeQUALCOMM INC·Filed 2006·Granted Jan 8, 2013·4 cites·35 claims
- 0663US12086600B2Branch target buffer with shared target bitsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 10, 2024·0 cites·18 claims
- 0760US12260220B2Accelerating fetch target queue (FTQ) processing in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Mar 25, 2025·0 cites·20 claims
- 0860US9411590B2Method to improve speed of executing return branch instructions in a processorQUALCOMM INC·Filed 2013·Granted Aug 9, 2016·1 cites·5 claims
- 0959US8291202B2Apparatus and methods for speculative interrupt vector prefetchingSTREETT DAREN EUGENE·Filed 2008·Granted Oct 16, 2012·3 cites·25 claims
- 1057US11995443B2Reuse of branch information queue entries for multiple instances of predicted control instructions in captured loops in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted May 28, 2024·0 cites·21 claims
- 1157US11928474B2Selectively updating branch predictors for loops executed from loop buffers in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Mar 12, 2024·0 cites·20 claims
- 1255US11487545B2Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Nov 1, 2022·0 cites·20 claims
- 1354US11915002B2Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadataMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Feb 27, 2024·0 cites·16 claims
- 1452US11789740B2Performing branch predictor training using probabilistic counter updates in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Oct 17, 2023·0 cites·15 claims
- 1549US9823929B2Optimizing performance for context-dependent instructionsQUALCOMM INC·Filed 2013·Granted Nov 21, 2017·0 cites·32 claims
- 1649US9317293B2Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Granted Apr 19, 2016·0 cites·28 claims
- 1749US2024192957A1Branch target buffer access systems and methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 1849US2024201998A1Performing storage-free instruction cache hit prediction in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 1948US2024168885A1Providing location-based prefetching in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 2043US2014281429A1Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2143US2022283811A1Loop buffering employing loop characteristic prediction in a processor for optimizing loop buffer performanceMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 2241US2014006752A1Qualifying Software Branch-Target Hints with Hardware-Based PredictionsMORROW MICHAEL WILLIAM·Filed 2012·Application pending·0 cites
- 2339US2019294443A1Providing early pipeline optimization of conditional instructions in processor-based systemsQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2436US2016350116A1Mitigating wrong-path effects in branch predictionQUALCOMM INC·Filed 2015·Application pending·0 cites
- 2535US2017083333A1Branch target instruction cache (btic) to store a conditional branch instructionQUALCOMM INC·Filed 2015·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Daren Eugene Streett files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →