Inventor · disambiguated record
Robert Boone
Also filed as: BOONE ROBERT · BOONE ROBERT E · BOONE ROBERT ELLIOTT
7 granted patents·7 pending applications·122 citations·filing 2001–2023
85Inventor score
Files withFREESCALE SEMICONDUCTOR INC7ASML NETHERLANDS BV2BOONE ROBERT E1LUCAS KEVIN D1LUCAS KEVIN DEAN1
Top patents by PatentIndex Score
14 records- 0191US8175737B2Method and apparatus for designing and integrated circuitLUCAS KEVIN DEAN·Filed 2006·Granted May 8, 2012·57 cites·20 claims
- 0284US6593226B2Method for adding features to a design layout and process for designing a maskMOTOROLA INC·Filed 2001·Granted Jul 15, 2003·34 cites·35 claims
- 0377US7962868B2Method for forming a semiconductor device using optical proximity correction for the optical lithographyFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 14, 2011·6 cites·20 claims
- 0473US8370773B2Method and apparatus for designing an integrated circuit using inverse lithography technologyFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 5, 2013·4 cites·19 claims
- 0567US7284231B2Layout modification using multilayer-based constraintsFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Oct 16, 2007·15 cites·22 claims
- 0660US8661393B2Method for analyzing placement context sensitivity of standard cellsBOONE ROBERT E·Filed 2012·Granted Feb 25, 2014·2 cites·20 claims
- 0759US2025284191A1Deep learning models for determining mask designs associated with semiconductor manufacturingASML NETHERLANDS BV·Filed 2023·Application pending·0 cites
- 0855US6818362B1Photolithography reticle designFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Nov 16, 2004·4 cites·22 claims
- 0944US2024119582A1A machine learning model using target pattern and reference layer pattern to determine optical proximity correction for maskASML NETHERLANDS BV·Filed 2022·Application pending·0 cites
- 1040US2010122224A1Method and apparatus for designing an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 1139US2008250374A1Method of Making an Integrated CircuitFREESCALE SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
- 1238US2008261375A1Method of Forming a Semiconductor Device Having a Dummy FeatureFREESCALE SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
- 1337US2006199087A1Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure fieldLUCAS KEVIN D·Filed 2005·Application pending·0 cites
- 1435US2004248016A1Method of designing a reticle and forming a semiconductor device therewithFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →