Inventor · disambiguated record
Thomas A. Ziaja
Also filed as: ZIAJA THOMAS · ZIAJA THOMAS A · ZIAJA THOMAS ALAN
15 granted patents·2 pending applications·182 citations·filing 2001–2024
92Inventor score
Files withSAMBANOVA SYSTEMS INC8SUN MICROSYSTEMS INC3ORACLE INT CORP2ZIAJA THOMAS A2GALA MURALI MOHAN REDDY1
Top patents by PatentIndex Score
17 records- 0198US7795899B1Enabling on-chip features via efusesORACLE AMERICA INC·Filed 2009·Granted Sep 14, 2010·73 cites·20 claims
- 0295US11428737B1Array of processor units with local BISTSAMBANOVA SYSTEMS INC·Filed 2021·Granted Aug 30, 2022·6 cites·28 claims
- 0394US7657807B1Integrated circuit with embedded test functionalitySUN MICROSYSTEMS INC·Filed 2005·Granted Feb 2, 2010·49 cites·22 claims
- 0492US11449404B1Built-in self-test for processor unit with combined memory and logicSAMBANOVA SYSTEMS INC·Filed 2021·Granted Sep 20, 2022·3 cites·22 claims
- 0592US11443822B2Method and circuit for row scannable latch arraySAMBANOVA SYSTEMS INC·Filed 2021·Granted Sep 13, 2022·4 cites·22 claims
- 0689US12243604B1Scannable memory array and a method for scanning memorySAMBANOVA SYSTEMS INC·Filed 2024·Granted Mar 4, 2025·2 cites·22 claims
- 0785US11961575B2Single “A” latch with an array of “B” latchesSAMBANOVA SYSTEMS INC·Filed 2022·Granted Apr 16, 2024·1 cites·5 claims
- 0882US11443823B2Method and circuit for scan dump of latch arraySAMBANOVA SYSTEMS INC·Filed 2021·Granted Sep 13, 2022·1 cites·20 claims
- 0982US9401223B2At-speed test of memory arrays using scanORACLE INT CORP·Filed 2014·Granted Jul 26, 2016·6 cites·18 claims
- 1071US7657805B2Integrated circuit with blocking pin to coordinate entry into test modeSUN MICROSYSTEMS INC·Filed 2007·Granted Feb 2, 2010·7 cites·20 claims
- 1171US6813201B2Automatic generation and validation of memory test modelsSUN MICROSYSTEMS INC·Filed 2001·Granted Nov 2, 2004·18 cites·28 claims
- 1268US8074133B2Method and apparatus for testing delay faultsZIAJA THOMAS A·Filed 2008·Granted Dec 6, 2011·7 cites·19 claims
- 1365US2024412797A1Fully Scannable Memory ArraysSAMBANOVA SYSTEMS INC·Filed 2023·Application pending·0 cites
- 1464US2024412798A1Method for Scanning a Memory ArraySAMBANOVA SYSTEMS INC·Filed 2024·Application pending·0 cites
- 1549US8214703B2Testing multi-core processorsGALA MURALI MOHAN REDDY·Filed 2009·Granted Jul 3, 2012·1 cites·20 claims
- 1649US8065572B2At-speed scan testing of memory arraysZIAJA THOMAS A·Filed 2009·Granted Nov 22, 2011·4 cites·18 claims
- 1733US10408876B2Memory circuit march testingORACLE INT CORP·Filed 2018·Granted Sep 10, 2019·0 cites·23 claims
Join the waitlist — get patent alerts
Get an alert when Thomas A. Ziaja files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →