Inventor · disambiguated record
Leelean Shu
Also filed as: SHU LEELEAN
7 granted patents·139 citations·filing 2011–2020
87Inventor score
Top patents by PatentIndex Score
7 records- 0195US9484076B1Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other featuresGSI TECHNOLOGY INC·Filed 2015·Granted Nov 1, 2016·23 cites·50 claims
- 0294US9159391B1Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other featuresGSI TECHNOLOGY INC·Filed 2013·Granted Oct 13, 2015·27 cites·23 claims
- 0393US9431079B1Systems and methods of memory and memory operation involving input latching, self-timing and/or other featuresGSI TECHNOLOGY INC·Filed 2013·Granted Aug 30, 2016·25 cites·12 claims
- 0493US8693236B2Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other featuresSHU LEELEAN·Filed 2012·Granted Apr 8, 2014·31 cites·159 claims
- 0591US10534836B2Four steps associative full adderGSI TECHNOLOGY INC·Filed 2017·Granted Jan 14, 2020·7 cites·20 claims
- 0691US8593860B2Systems and methods of sectioned bit line memory arraysSHU LEELEAN·Filed 2011·Granted Nov 26, 2013·26 cites·58 claims
- 0763US11604850B2In-memory full adderGSI TECHNOLOGY INC·Filed 2020·Granted Mar 14, 2023·0 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →