Inventor · disambiguated record
Timothy Michael Burks
Also filed as: BURKS TIMOTHY M · BURKS TIMOTHY MICHAEL
11 granted patents·469 citations·filing 1996–2015
92Inventor score
Top patents by PatentIndex Score
11 records- 0195US8898748B2Remote verification for configuration updatesBURKS TIMOTHY MICHAEL·Filed 2009·Granted Nov 25, 2014·131 cites·21 claims
- 0291US7103863B2Representing the design of a sub-module in a hierarchical integrated circuit design and analysis systemMAGMA DESIGN AUTOMATION INC·Filed 2002·Granted Sep 5, 2006·106 cites·68 claims
- 0388US6845494B2Method for generating design constraints for modules in a hierarchical integrated circuit design systemMAGMA DESIGN AUTOMATION INC·Filed 2002·Granted Jan 18, 2005·77 cites·50 claims
- 0485US9203698B2Remote verification for configuration updatesMOBILE IRON INC·Filed 2014·Granted Dec 1, 2015·5 cites·20 claims
- 0576US9559907B2Remote verification for configuration updatesMOBILE IRON INC·Filed 2015·Granted Jan 31, 2017·2 cites·20 claims
- 0673US7346874B1Parametric timing analysisMAGMA DESIGN AUTOMATION INC·Filed 2005·Granted Mar 18, 2008·6 cites·12 claims
- 0772US7970590B1Parametric timing analysisMAGMA DESIGN AUTOMATION INC·Filed 2008·Granted Jun 28, 2011·5 cites·15 claims
- 0866US6014510AMethod for performing timing analysis of a clock circuitIBM·Filed 1996·Granted Jan 11, 2000·50 cites·27 claims
- 0960US6185723B1Method for performing timing analysis of a clock-shaping circuitIBM·Filed 1996·Granted Feb 6, 2001·37 cites·27 claims
- 1058US5946475AMethod for performing transistor-level static timing analysis of a logic circuitIBM·Filed 1997·Granted Aug 31, 1999·34 cites·19 claims
- 1139US6601220B1Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation pathsIBM·Filed 1996·Granted Jul 29, 2003·16 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →