Inventor · disambiguated record
Christopher J. Pass
Also filed as: PASS CHRISTOPHER · PASS CHRISTOPHER J
15 granted patents·287 citations·filing 1996–2018
92Inventor score
Top patents by PatentIndex Score
15 records- 0199US5949710AProgrammable interconnect junctionALTERA CORP·Filed 1996·Granted Sep 7, 1999·191 cites·48 claims
- 0294US10090840B1Integrated circuits with programmable non-volatile resistive switch elementsINTEL CORP·Filed 2017·Granted Oct 2, 2018·12 cites·16 claims
- 0388US10573375B1Methods and circuitry for programming non-volatile resistive switches using varistorsINTEL CORP·Filed 2018·Granted Feb 25, 2020·8 cites·20 claims
- 0481US7759226B1Electrical fuse with sacrificial contactALTERA CORP·Filed 2005·Granted Jul 20, 2010·9 cites·3 claims
- 0581US6956165B1Underfill for maximum flip chip package reliabilityALTERA CORP·Filed 2004·Granted Oct 18, 2005·31 cites·18 claims
- 0673US6122209AMethod of margin testing programmable interconnect cellALTERA CORP·Filed 1999·Granted Sep 19, 2000·18 cites·15 claims
- 0763US7883946B1Angled implantation for deep submicron device optimizationALTERA CORP·Filed 2008·Granted Feb 8, 2011·1 cites·29 claims
- 0863US6573138B1Nonvolatile memory cell with low doping regionALTERA CORP·Filed 1999·Granted Jun 3, 2003·12 cites·42 claims
- 0960US10447275B2Integrated circuits with programmable non-volatile resistive switch elementsINTEL CORP·Filed 2018·Granted Oct 15, 2019·0 cites·19 claims
- 1059US10269426B2Integrated circuits with complementary non-volatile resistive memory elementsINTEL CORP·Filed 2017·Granted Apr 23, 2019·1 cites·14 claims
- 1155US6828620B2Nonvolatile memory cell with low doping regionALTERA CORP·Filed 2003·Granted Dec 7, 2004·4 cites·16 claims
- 1248US8519403B1Angled implantation for deep submicron device optimizationHSU CHE TA·Filed 2011·Granted Aug 27, 2013·0 cites·8 claims
- 1346US10037992B1Methods and apparatuses for optimizing power and functionality in transistorsALTERA CORP·Filed 2014·Granted Jul 31, 2018·0 cites·20 claims
- 1444US8492798B1Electrical fuse with sacrificial contactLEE SHIH-LIN S·Filed 2010·Granted Jul 23, 2013·0 cites·2 claims
- 1536US8912104B1Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimizationRATAKONDA DEEPA·Filed 2011·Granted Dec 16, 2014·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →