Inventor · disambiguated record
Chung Kwang Christopher Tan
Also filed as: TAN CHUNG KWANG · TAN CHUNG KWANG CHRISTOPHER
14 granted patents·3 pending applications·7 citations·filing 2017–2025
87Inventor score
Technology areasH10W
Files withINTEL CORP17
Top patents by PatentIndex Score
17 records- 0193US11676891B2Method to enable 30 microns pitch EMIB or belowINTEL CORP·Filed 2021·Granted Jun 13, 2023·2 cites·20 claims
- 0286US11088062B2Method to enable 30 microns pitch EMIB or belowINTEL CORP·Filed 2017·Granted Aug 10, 2021·4 cites·14 claims
- 0386US2025323166A1Lithographic cavity formation to enable emib bump pitch scalingINTEL CORP·Filed 2025·Application pending·0 cites
- 0484US2025069902A1Integrated circuit package supportsINTEL CORP·Filed 2024·Application pending·0 cites
- 0583US12354963B2Lithographic cavity formation to enable EMIB bump pitch scalingINTEL CORP·Filed 2024·Granted Jul 8, 2025·0 cites·19 claims
- 0683US12334443B2Lithographic cavity formation to enable EMIB bump pitch scalingINTEL CORP·Filed 2024·Granted Jun 17, 2025·0 cites·18 claims
- 0783US12176223B2Integrated circuit package supportsINTEL CORP·Filed 2023·Granted Dec 24, 2024·0 cites·20 claims
- 0876US12230563B2Method to enable 30 microns pitch EMIB or belowINTEL CORP·Filed 2022·Granted Feb 18, 2025·0 cites·21 claims
- 0976US11854834B2Integrated circuit package supportsINTEL CORP·Filed 2022·Granted Dec 26, 2023·0 cites·17 claims
- 1075US11929330B2Lithographic cavity formation to enable EMIB bump pitch scalingINTEL CORP·Filed 2022·Granted Mar 12, 2024·0 cites·20 claims
- 1175US2025149433A1New method to enable 30 microns pitch emib or belowINTEL CORP·Filed 2025·Application pending·0 cites
- 1272US11322444B2Lithographic cavity formation to enable EMIB bump pitch scalingINTEL CORP·Filed 2018·Granted May 3, 2022·1 cites·16 claims
- 1369US11721631B2Via structures having tapered profiles for embedded interconnect bridge substratesINTEL CORP·Filed 2022·Granted Aug 8, 2023·0 cites·25 claims
- 1460US11309192B2Integrated circuit package supportsINTEL CORP·Filed 2018·Granted Apr 19, 2022·0 cites·25 claims
- 1558US11264307B2Dual-damascene zero-misalignment-via process for semiconductor packagingINTEL CORP·Filed 2019·Granted Mar 1, 2022·0 cites·20 claims
- 1653US11373951B2Via structures having tapered profiles for embedded interconnect bridge substratesINTEL CORP·Filed 2018·Granted Jun 28, 2022·0 cites·17 claims
- 1751US10403564B2Dual-damascene zero-misalignment-via process for semiconductor packagingINTEL CORP·Filed 2017·Granted Sep 3, 2019·0 cites·36 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →