Inventor · disambiguated record
Sang Hyeon Baeg
Also filed as: BAEG SANG HYEON
10 granted patents·102 citations·filing 1996–2011
89Inventor score
Top patents by PatentIndex Score
10 records- 0189US8856704B2Layout library of flip-flop circuitBAEG SANG HYEON·Filed 2011·Granted Oct 7, 2014·21 cites·13 claims
- 0287US7269770B1AC coupled line testing using boundary scan test methodologyCISCO TECH INC·Filed 2007·Granted Sep 11, 2007·14 cites·11 claims
- 0373US7487412B2Test buffer design and interface mechanism for differential receiver AC/DC boundary scan testCISCO TECH INC·Filed 2006·Granted Feb 3, 2009·6 cites·18 claims
- 0470US7174492B1AC coupled line testing using boundary scan test methodologyCISCO TECH INC·Filed 2001·Granted Feb 6, 2007·14 cites·13 claims
- 0555US7089463B1Test buffer design and interface mechanism for differential receiver AC/DC boundary scan testCISCO TECH INC·Filed 2002·Granted Aug 8, 2006·6 cites·15 claims
- 0654US7089470B1Programmable test pattern and capture mechanism for boundary scanCISCO TECH INC·Filed 2003·Granted Aug 8, 2006·7 cites·11 claims
- 0753US6019502ATest circuits and methods for built-in testing integrated devicesSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Feb 1, 2000·15 cites·15 claims
- 0847US5754758ASerial memory interface using interlaced scanSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted May 19, 1998·13 cites·12 claims
- 0941US8664971B2Method of testing functioning of a semiconductor deviceBAEG SANG HYEON·Filed 2008·Granted Mar 4, 2014·0 cites·6 claims
- 1032US5706293AMethod of testing single-order address memorySAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Jan 6, 1998·6 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →