Inventor · disambiguated record
Haining Yang
Also filed as: YANG HAINING · YANG HAINING S · YANG HAINING SAM
280 granted patents·94 pending applications·3,392 citations·filing 1998–2023
99Inventor score
Top patents by PatentIndex Score
374 records- 0198US11393819B2Semiconductor device implemented with buried railsQUALCOMM INC·Filed 2020·Granted Jul 19, 2022·7 cites·18 claims
- 0298US7816231B2Device structures including backside contacts, and methods for forming sameIBM·Filed 2006·Granted Oct 19, 2010·55 cites·6 claims
- 0398US7791109B2Metal silicide alloy local interconnectIBM·Filed 2007·Granted Sep 7, 2010·109 cites·11 claims
- 0498US7767099B2Sub-lithographic interconnect patterning using self-assembling polymersIBM·Filed 2007·Granted Aug 3, 2010·73 cites·24 claims
- 0598US7625790B2FinFET with sublithographic fin widthIBM·Filed 2007·Granted Dec 1, 2009·120 cites·11 claims
- 0698US7605081B2Sub-lithographic feature patterning using self-aligned self-assembly polymersIBM·Filed 2006·Granted Oct 20, 2009·100 cites·10 claims
- 0798US7592247B2Sub-lithographic local interconnects, and methods for forming sameIBM·Filed 2006·Granted Sep 22, 2009·75 cites·1 claims
- 0898US7557424B2Reversible electric fuse and antifuse structures for semiconductor devicesIBM·Filed 2007·Granted Jul 7, 2009·75 cites·16 claims
- 0998US7553760B2Sub-lithographic nano interconnect structures, and method for forming sameIBM·Filed 2006·Granted Jun 30, 2009·119 cites·1 claims
- 1098US6891192B2Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2003·Granted May 10, 2005·179 cites·11 claims
- 1198US6881635B1Strained silicon NMOS devices with embedded source/drainIBM·Filed 2004·Granted Apr 19, 2005·176 cites·13 claims
- 1297US10622479B1Circuits employing a double diffusion break (DDB) and single diffusion break (SDB) in different type diffusion region(s), and related fabrication methodsQUALCOMM INC·Filed 2018·Granted Apr 14, 2020·17 cites·26 claims
- 1397US9698232B2Conductive cap for metal-gate transistorQUALCOMM INC·Filed 2015·Granted Jul 4, 2017·18 cites·26 claims
- 1497US7514339B2Method for fabricating shallow trench isolation structures using diblock copolymer patterningIBM·Filed 2007·Granted Apr 7, 2009·57 cites·20 claims
- 1597US6524867B2Method for forming platinum-rhodium stack as an oxygen barrierMICRON TECHNOLOGY INC·Filed 2000·Granted Feb 25, 2003·121 cites·3 claims
- 1696US9653466B2FinFET device and method of making the sameQUALCOMM INC·Filed 2015·Granted May 16, 2017·15 cites·24 claims
- 1796US8083958B2Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniquesLI WAI-KIN·Filed 2007·Granted Dec 27, 2011·63 cites·24 claims
- 1896US7867832B2Electrical fuse and method of makingIBM·Filed 2008·Granted Jan 11, 2011·31 cites·19 claims
- 1996US7781847B2Device patterned with sub-lithographic features with variable widthsIBM·Filed 2008·Granted Aug 24, 2010·35 cites·10 claims
- 2096US6518610B2Rhodium-rich oxygen barriersMICRON TECHNOLOGY INC·Filed 2001·Granted Feb 11, 2003·104 cites·23 claims
- 2195US10996399B2Space-division multiplexed reconfigurable, wavelength selective switchROADMAP SYSTEMS LTD·Filed 2017·Granted May 4, 2021·18 cites·15 claims
- 2295US9537007B2FinFET with cut gate stressorQUALCOMM INC·Filed 2015·Granted Jan 3, 2017·12 cites·19 claims
- 2395US7984408B2Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier loweringIBM·Filed 2007·Granted Jul 19, 2011·36 cites·8 claims
- 2495US7973409B2Hybrid interconnect structure for performance improvement and reliability enhancementIBM·Filed 2007·Granted Jul 5, 2011·24 cites·9 claims
- 2595US7737501B2FinFET SRAM with asymmetric gate and method of manufacture thereofIBM·Filed 2007·Granted Jun 15, 2010·33 cites·15 claims
- 2695US6939814B2Increasing carrier mobility in NFET and PFET transistors on a common waferIBM·Filed 2003·Granted Sep 6, 2005·97 cites·11 claims
- 2794US10950609B2Gate-all-around (GAA) and fin field-effect transistor (FinFet) hybrid static random-access memory (SRAM)QUALCOMM INC·Filed 2019·Granted Mar 16, 2021·8 cites·16 claims
- 2894US7696085B2Dual damascene metal interconnect structure having a self-aligned viaIBM·Filed 2008·Granted Apr 13, 2010·25 cites·13 claims
- 2993US10825536B1Programmable circuits for performing machine learning operations on edge devicesQUALCOMM INC·Filed 2019·Granted Nov 3, 2020·19 cites·30 claims
- 3093US7531423B2Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the sameIBM·Filed 2005·Granted May 12, 2009·23 cites·3 claims
- 3193US7485508B2Two-sided semiconductor-on-insulator structures and methods of manufacturing the sameIBM·Filed 2007·Granted Feb 3, 2009·28 cites·20 claims
- 3293US7101744B1Method for forming self-aligned, dual silicon nitride liner for CMOS devicesIBM·Filed 2005·Granted Sep 5, 2006·28 cites·20 claims
- 3392US8889504B2Semiconductor devices having tensile and/or compressive stress and methods of manufacturingDYER THOMAS W·Filed 2012·Granted Nov 18, 2014·9 cites·9 claims
- 3492US7915691B2High density SRAM cell with hybrid devicesIBM·Filed 2007·Granted Mar 29, 2011·19 cites·20 claims
- 3592US7732872B2Integration scheme for multiple metal gate work function structuresIBM·Filed 2007·Granted Jun 8, 2010·24 cites·14 claims
- 3692US7384852B2Sub-lithographic gate length transistor using self-assembling polymersIBM·Filed 2006·Granted Jun 10, 2008·18 cites·8 claims
- 3792US7361539B2Dual stress linerIBM·Filed 2006·Granted Apr 22, 2008·19 cites·11 claims
- 3892US7291528B2Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2005·Granted Nov 6, 2007·16 cites·17 claims
- 3991US9633996B1High density area efficient thin-oxide decoupling capacitor using conductive gate resistorQUALCOMM INC·Filed 2016·Granted Apr 25, 2017·8 cites·25 claims
- 4091US9040960B2Heterojunction tunneling field effect transistors, and methods for fabricating the sameCHEN XIANGDONG·Filed 2012·Granted May 26, 2015·9 cites·7 claims
- 4191US7741721B2Electrical fuses and resistors having sublithographic dimensionsIBM·Filed 2007·Granted Jun 22, 2010·14 cites·6 claims
- 4291US7709317B2Method to increase strain enhancement with spacerless FET and dual liner processIBM·Filed 2005·Granted May 4, 2010·15 cites·12 claims
- 4391US7002209B2MOSFET structure with high mechanical stress in the channelIBM·Filed 2004·Granted Feb 21, 2006·61 cites·20 claims
- 4491US6906360B2Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regionsIBM·Filed 2003·Granted Jun 14, 2005·55 cites·12 claims
- 4590US10431686B1Integrated circuit (IC) employing a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformityQUALCOMM INC·Filed 2018·Granted Oct 1, 2019·6 cites·28 claims
- 4690US7678658B2Structure and method for improved SRAM interconnectIBM·Filed 2008·Granted Mar 16, 2010·18 cites·9 claims
- 4790US7635620B2Semiconductor device structure having enhanced performance FET deviceIBM·Filed 2006·Granted Dec 22, 2009·16 cites·14 claims
- 4890US7504336B2Methods for forming CMOS devices with intrinsically stressed metal silicide layersIBM·Filed 2006·Granted Mar 17, 2009·16 cites·18 claims
- 4990US6946709B2Complementary transistors having different source and drain extension spacing controlled by different spacer sizesIBM·Filed 2003·Granted Sep 20, 2005·44 cites·17 claims
- 5090US6660581B1Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devicesIBM·Filed 2003·Granted Dec 9, 2003·55 cites·20 claims
Showing the top 50 of 374 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Haining Yang files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →