Inventor · disambiguated record
Michael Laisne
Also filed as: LAISNE MICHAEL
9 granted patents·8 pending applications·56 citations·filing 2006–2020
85Inventor score
Files withQUALCOMM INC8LAISNE MICHAEL3ARSLAN BARIS1DIALOG SEMICONDUCTOR INC1DIALOG SEMICONDUCTOR UK LTD1
Top patents by PatentIndex Score
17 records- 0194US11056210B1Electrical circuit comprising a trim circuitDIALOG SEMICONDUCTOR UK LTD·Filed 2020·Granted Jul 6, 2021·4 cites·27 claims
- 0292US8384417B2Systems and methods utilizing redundancy in semiconductor chip interconnectsQUALCOMM INC·Filed 2009·Granted Feb 26, 2013·28 cites·32 claims
- 0377US9316690B2Data recirculation in configured scan pathsZUO SONGLIN·Filed 2011·Granted Apr 19, 2016·7 cites·19 claims
- 0475US9024315B2Daisy chain connection for testing continuity in a semiconductor dieQUALCOMM INC·Filed 2013·Granted May 5, 2015·5 cites·42 claims
- 0565US7750660B2Integrated circuit with improved test capability via reduced pin countQUALCOMM INC·Filed 2006·Granted Jul 6, 2010·6 cites·7 claims
- 0658US7932736B2Integrated circuit with improved test capability via reduced pin countQUALCOMM INC·Filed 2010·Granted Apr 26, 2011·1 cites·9 claims
- 0757US8420410B2Techniques providing fiducial markers for failure analysisLAISNE MICHAEL·Filed 2010·Granted Apr 16, 2013·1 cites·24 claims
- 0852US8159255B2Methodologies and tool set for IDDQ verification, debugging and failure diagnosisLAISNE MICHAEL·Filed 2008·Granted Apr 17, 2012·4 cites·75 claims
- 0946US10135686B2Communication interfaceDIALOG SEMICONDUCTOR INC·Filed 2017·Granted Nov 20, 2018·0 cites·14 claims
- 1045US2015199461A1Method and apparatus for timing verificationQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1139US2012324302A1Integrated circuit for testing using a high-speed input/output interfaceARSLAN BARIS·Filed 2012·Application pending·0 cites
- 1235US2012110531A1Defect and yield prediction for segments of an integrated circuitLIAO HONGMEI·Filed 2010·Application pending·0 cites
- 1335US2013297981A1Low cost high throughput tsv/microbump probeGU SHIQUN·Filed 2012·Application pending·0 cites
- 1434US2011307748A1Techniques for error diagnosis in vlsi systemsLAISNE MICHAEL·Filed 2011·Application pending·0 cites
- 1530US2011270548A1Automated verification and estimation of quiescent power supply currentQUALCOMM INC·Filed 2011·Application pending·0 cites
- 1628US2016349320A1Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniquesQUALCOMM INC·Filed 2015·Application pending·0 cites
- 1726US2017010325A1Adaptive test time reductionQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →