Inventor · disambiguated record
Dennis R. Blankenship
Also filed as: BLANKENSHIP DENNIS · BLANKENSHIP DENNIS R
9 granted patents·165 citations·filing 1994–2014
89Inventor score
Files withMITSUBISHI SEMICONDUCTOR AM5MICRON TECHNOLOGY INC2MITSUBISHI ELECTRONICS AMERICA1QIMONDA AG1
Top patents by PatentIndex Score
9 records- 0191US7872936B2System and method for packaged memoryQIMONDA AG·Filed 2008·Granted Jan 18, 2011·27 cites·31 claims
- 0280US5486785ACMOS level shifter with feedforward control to prevent latching in a wrong logic stateMITSUBISHI SEMICONDUCTOR AM·Filed 1994·Granted Jan 23, 1996·37 cites·13 claims
- 0370US5680365AShared dram I/O databus for high speed operationMITSUBISHI SEMICONDUCTOR AM·Filed 1996·Granted Oct 21, 1997·33 cites·11 claims
- 0468US5798972AHigh-speed main amplifier with reduced access and output disable time periodsMITSUBISHI SEMICONDUCTOR AM·Filed 1996·Granted Aug 25, 1998·29 cites·16 claims
- 0563US8817547B2Apparatuses and methods for unit identification in a master/slave memory stackMICRON TECHNOLOGY INC·Filed 2012·Granted Aug 26, 2014·2 cites·23 claims
- 0655US6157990AIndependent chip select for SRAM and DRAM in a multi-port RAMMITSUBISHI ELECTRONICS AMERICA·Filed 1998·Granted Dec 5, 2000·18 cites·11 claims
- 0746US9305625B2Apparatuses and methods for unit identification in a master/slave memory stackMICRON TECHNOLOGY INC·Filed 2014·Granted Apr 5, 2016·0 cites·20 claims
- 0846US5838606AThree-transistor static storage cellMITSUBISHI SEMICONDUCTOR AM·Filed 1997·Granted Nov 17, 1998·11 cites·12 claims
- 0941US5784329ALatched DRAM write bus for quickly clearing DRAM array with minimum power usageMITSUBISHI SEMICONDUCTOR AM·Filed 1997·Granted Jul 21, 1998·8 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →