Inventor · disambiguated record
Kenneth D. Klapproth
Also filed as: KLAPPROTH KENNETH · KLAPPROTH KENNETH D · KLAPPROTH KENNETH DOUGLAS
29 granted patents·4 pending applications·153 citations·filing 1998–2024
95Inventor score
Top patents by PatentIndex Score
33 records- 0179US10956637B2Placement-driven generation of error detecting structures in integrated circuitsIBM·Filed 2019·Granted Mar 23, 2021·2 cites·20 claims
- 0279US9734110B2Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessingIBM·Filed 2015·Granted Aug 15, 2017·3 cites·15 claims
- 0377US10915461B2Multilevel cache eviction managementIBM·Filed 2019·Granted Feb 9, 2021·2 cites·14 claims
- 0477US10802966B2Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelizationIBM·Filed 2019·Granted Oct 13, 2020·2 cites·20 claims
- 0577US10540251B2Accuracy sensitive performance countersIBM·Filed 2017·Granted Jan 21, 2020·2 cites·20 claims
- 0676US10325049B2Placement-driven generation of error detecting structures in integrated circuitsIBM·Filed 2017·Granted Jun 18, 2019·2 cites·20 claims
- 0775US9003127B2Storing data in a system memory for a subsequent cache flushIBM·Filed 2013·Granted Apr 7, 2015·3 cites·9 claims
- 0874US8458405B2Cache bank modeling with variable access and busy timesBRONSON TIMOTHY C·Filed 2010·Granted Jun 4, 2013·4 cites·20 claims
- 0969US8930616B2System refresh in cache memoryIBM·Filed 2012·Granted Jan 6, 2015·2 cites·20 claims
- 1069US6816826B1Fully exhibiting asynchronous behavior in a logic network simulationIBM·Filed 2000·Granted Nov 9, 2004·15 cites·18 claims
- 1167US6904585B2Method for identification and removal of non-timing critical wire routes from congestion regionIBM·Filed 2003·Granted Jun 7, 2005·13 cites·9 claims
- 1264US6484220B1Transfer of data between processors in a multi-processor systemIBM·Filed 1999·Granted Nov 19, 2002·42 cites·35 claims
- 1360US10884890B2Accuracy sensitive performance countersIBM·Filed 2019·Granted Jan 5, 2021·0 cites·20 claims
- 1460US8478920B2Controlling data stream interruptions on a shared interfaceDRAPALA GARRETT M·Filed 2010·Granted Jul 2, 2013·1 cites·16 claims
- 1558US12475079B1Bidirectional ring-based interconnection networks having a cross bar for multiprocessorsIBM·Filed 2024·Granted Nov 18, 2025·0 cites·20 claims
- 1657US10489292B2Ownership tracking updates across multiple simultaneous operationsIBM·Filed 2017·Granted Nov 26, 2019·0 cites·6 claims
- 1757US6134684AMethod and system for error detection in test units utilizing pseudo-random dataIBM·Filed 1998·Granted Oct 17, 2000·31 cites·16 claims
- 1855US10482015B2Ownership tracking updates across multiple simultaneous operationsIBM·Filed 2017·Granted Nov 19, 2019·0 cites·11 claims
- 1953US8706972B2Dynamic mode transitions for cache instructionsIBM·Filed 2012·Granted Apr 22, 2014·0 cites·7 claims
- 2051US7529799B2Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor systemIBM·Filed 2002·Granted May 5, 2009·2 cites·21 claims
- 2151US2024176636A1Deadlock and hang avoidance in a large distributed computer systemIBM·Filed 2022·Application pending·0 cites
- 2250US8990507B2Storing data in a system memory for a subsequent cache flushBLAKE MICHAEL A·Filed 2012·Granted Mar 24, 2015·0 cites·5 claims
- 2349US6580288B1Multi-property microprocessor with no additional logic overhead to shared pinsIBM·Filed 1999·Granted Jun 17, 2003·20 cites·26 claims
- 2446US10831661B2Coherent cache with simultaneous data requests in same addressable indexIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 2546US8635409B2Dynamic mode transitions for cache instructionsDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Jan 21, 2014·0 cites·15 claims
- 2645US2023318979A1Bidirectional ring-based interconnection networks for multiprocessorsIBM·Filed 2022·Application pending·0 cites
- 2743US10379776B2Operation interlocking in an address-sliced cache systemIBM·Filed 2017·Granted Aug 13, 2019·0 cites·11 claims
- 2843US8639887B2Dynamically altering a pipeline controller mode based on resource availabilityBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Jan 28, 2014·0 cites·22 claims
- 2943US2011320699A1System Refresh in Cache MemoryBLAKE MICHAEL·Filed 2010·Application pending·0 cites
- 3041US8291157B2Concurrent refresh in cache memoryBRONSON TIMOTHY C·Filed 2010·Granted Oct 16, 2012·0 cites·22 claims
- 3140US2018365070A1Dynamic throttling of broadcasts in a tiered multi-node symmetric multiprocessing computer systemIBM·Filed 2017·Application pending·0 cites
- 3236US11221794B2Memory array element sparingIBM·Filed 2019·Granted Jan 11, 2022·0 cites·20 claims
- 3335US6510471B1Method for choosing device among plurality of devices based on coherncy status of device's data and if device supports higher-performance transactionsIBM·Filed 1999·Granted Jan 21, 2003·7 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →