Inventor · disambiguated record
Neal Berger
Also filed as: BERGER NEAL
72 granted patents·2 pending applications·649 citations·filing 1995–2024
99Inventor score
Files withSPIN TRANSFER TECH INC19SPIN MEMORY INC15ZENO SEMICONDUCTOR INC9INTEGRATED SILICON SOLUTION CAYMAN INC7BERGER NEAL5
Top patents by PatentIndex Score
74 records- 0199US11250905B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2021·Granted Feb 15, 2022·9 cites·20 claims
- 0299US10923183B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2020·Granted Feb 16, 2021·9 cites·20 claims
- 0398US10115446B1Spin transfer torque MRAM device with error bufferSPIN TRANSFER TECH INC·Filed 2016·Granted Oct 30, 2018·53 cites·22 claims
- 0498US9496053B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2015·Granted Nov 15, 2016·29 cites·20 claims
- 0597US11715515B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2022·Granted Aug 1, 2023·3 cites·20 claims
- 0697US10163479B2Method and apparatus for bipolar memory write-verifySPIN TRANSFER TECH INC·Filed 2016·Granted Dec 25, 2018·50 cites·23 claims
- 0797US10115451B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2017·Granted Oct 30, 2018·16 cites·11 claims
- 0897US9799392B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2016·Granted Oct 24, 2017·21 cites·10 claims
- 0997US8441844B2Method for writing in a MRAM-based memory device with reduced power consumptionEL BARAJI MOURAD·Filed 2011·Granted May 14, 2013·47 cites·8 claims
- 1096US10580482B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2018·Granted Mar 3, 2020·12 cites·10 claims
- 1193US5594366AProgrammable logic device with regional and universal signal routingATMEL CORP·Filed 1995·Granted Jan 14, 1997·143 cites·9 claims
- 1291US5968196AConfiguration control in a programmable logic device using non-volatile elementsATMEL CORP·Filed 1998·Granted Oct 19, 1999·95 cites·18 claims
- 1390US10699761B2Word line decoder memory architectureSPIN MEMORY INC·Filed 2018·Granted Jun 30, 2020·9 cites·9 claims
- 1486US8031519B2Shared line magnetic random access memory cellsCROCUS TECHNOLOGY SA·Filed 2009·Granted Oct 4, 2011·17 cites·14 claims
- 1585US10460781B2Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bankSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 29, 2019·6 cites·17 claims
- 1685US8717794B2Apparatus, system, and method for matching patterns with an ultra fast check engineCAMBOU BERTRAND F·Filed 2011·Granted May 6, 2014·8 cites·17 claims
- 1785US2024404585A1Memory Device Comprising Electrically Floating Body TransistorZENO SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 1884US10347314B2Method and apparatus for bipolar memory write-verifySPIN TRANSFER TECH INC·Filed 2017·Granted Jul 9, 2019·6 cites·21 claims
- 1981US12094526B2Memory device comprising electrically floating body transistorZENO SEMICONDUCTOR INC·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 2078US8542525B2MRAM-based memory device with rotated gateBERGER NEAL·Filed 2011·Granted Sep 24, 2013·7 cites·15 claims
- 2178US5848026AIntegrated circuit with flag register for block selection of nonvolatile cells for bulk operationsATMEL CORP·Filed 1997·Granted Dec 8, 1998·46 cites·17 claims
- 2277US8611140B2Magnetic random access memory devices including shared heating strapsEL BARAJI MOURAD·Filed 2011·Granted Dec 17, 2013·6 cites·25 claims
- 2374US8169815B2System and method for writing data to magnetoresistive random access memory cellsJAVERLIAC VIRGILE·Filed 2009·Granted May 1, 2012·9 cites·12 claims
- 2473US10395711B2Perpendicular source and bit lines for an MRAM arraySPIN TRANSFER TECH INC·Filed 2017·Granted Aug 27, 2019·3 cites·11 claims
- 2573US8218349B2Non-volatile logic devices using magnetic tunnel junctionsBERGER NEAL·Filed 2010·Granted Jul 10, 2012·5 cites·15 claims
- 2671US8824202B2Self-referenced magnetic random access memory cellsBERGER NEAL·Filed 2010·Granted Sep 2, 2014·4 cites·14 claims
- 2771US8611141B2Magnetic random access memory devices including heating strapsBARAJI MOURAD EL·Filed 2011·Granted Dec 17, 2013·8 cites·18 claims
- 2870US11119910B2Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segmentsSPIN MEMORY INC·Filed 2019·Granted Sep 14, 2021·2 cites·15 claims
- 2967US11941299B2MRAM access coordination systems and methods via pipeline in parallelINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2022·Granted Mar 26, 2024·0 cites·7 claims
- 3067US10446210B2Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registersSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 15, 2019·2 cites·20 claims
- 3167US10437723B2Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory deviceSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 8, 2019·2 cites·20 claims
- 3264US8467234B2Magnetic random access memory devices configured for self-referenced read operationBERGER NEAL·Filed 2011·Granted Jun 18, 2013·3 cites·20 claims
- 3363US11586553B2Error cache system with coarse and fine segments for power optimizationINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2021·Granted Feb 21, 2023·0 cites·20 claims
- 3463US10930332B2Memory array with individually trimmable sense amplifiersSPIN MEMORY INC·Filed 2019·Granted Feb 23, 2021·1 cites·18 claims
- 3563US10366775B2Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operationSPIN TRANSFER TECH INC·Filed 2017·Granted Jul 30, 2019·1 cites·24 claims
- 3662US11334288B2MRAM access coordination systems and methods with a plurality of pipelinesINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2019·Granted May 17, 2022·0 cites·16 claims
- 3761US10489245B2Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct themSPIN TRANSFER TECH INC·Filed 2017·Granted Nov 26, 2019·1 cites·20 claims
- 3861US10360962B1Memory array with individually trimmable sense amplifiersSPIN TRANSFER TECH INC·Filed 2017·Granted Jul 23, 2019·1 cites·15 claims
- 3960US10546625B2Method of optimizing write voltage based on error buffer occupancySPIN MEMORY INC·Filed 2018·Granted Jan 28, 2020·1 cites·21 claims
- 4060US10192602B2Smart cache design to prevent overflow for a memory device with a dynamic redundancy registerSPIN TRANSFER TECH INC·Filed 2017·Granted Jan 29, 2019·1 cites·23 claims
- 4160US8576615B2Magnetic random access memory devices including multi-bit cellsEL BARAJI MOURAD·Filed 2011·Granted Nov 5, 2013·3 cites·20 claims
- 4259US10192601B2Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registersSPIN TRANSFER TECH INC·Filed 2017·Granted Jan 29, 2019·1 cites·21 claims
- 4358US11580014B2Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segmentsINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2021·Granted Feb 14, 2023·0 cites·20 claims
- 4455US11423965B2Word line decoder memory architectureINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Aug 23, 2022·0 cites·12 claims
- 4555US11386010B2Circuit engine for managing memory meta-stabilityINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Jul 12, 2022·0 cites·20 claims
- 4655US11119936B2Error cache system with coarse and fine segments for power optimizationSPIN MEMORY INC·Filed 2019·Granted Sep 14, 2021·0 cites·20 claims
- 4754US8902643B2Apparatus, system, and method for writing multiple magnetic random access memory cells with a single field lineCROCUS TECHNOLOGY INC·Filed 2012·Granted Dec 2, 2014·1 cites·20 claims
- 4853US11010294B2MRAM noise mitigation for write operations with simultaneous background operationsSPIN MEMORY INC·Filed 2019·Granted May 18, 2021·0 cites·20 claims
- 4953US9218879B2Apparatus, system, and method for matching patterns with an ultra fast check engine based on flash cellsCAMBOU BERTRAND F·Filed 2011·Granted Dec 22, 2015·1 cites·23 claims
- 5053US9054029B2Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cellsCROCUS TECHNOLOGY INC·Filed 2014·Granted Jun 9, 2015·0 cites·14 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →