Inventor · disambiguated record
Steven M. Douskey
Also filed as: DOUSKEY STEVEN M · DOUSKEY STEVEN MICHAEL
78 granted patents·2 pending applications·1,100 citations·filing 1989–2020
99Inventor score
Top patents by PatentIndex Score
80 records- 0194US9404969B1Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad diesCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Aug 2, 2016·25 cites·18 claims
- 0294US6158032AData processing system, circuit arrangement and program product including multi-path scan interface and methods thereofIBM·Filed 1998·Granted Dec 5, 2000·146 cites·37 claims
- 0393US8856720B2Test coverage of integrated circuits with masking pattern selectionIBM·Filed 2013·Granted Oct 7, 2014·9 cites·7 claims
- 0493US6807645B2Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failuresIBM·Filed 2002·Granted Oct 19, 2004·66 cites·32 claims
- 0593US6115763AMulti-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unitIBM·Filed 1998·Granted Sep 5, 2000·370 cites·67 claims
- 0692US5717701AApparatus and method for testing interconnections between semiconductor devicesIBM·Filed 1996·Granted Feb 10, 1998·98 cites·22 claims
- 0791US9103879B2Test coverage of integrated circuits with test vector input spreadingIBM·Filed 2013·Granted Aug 11, 2015·9 cites·5 claims
- 0890US10060971B2Adjusting latency in a scan cellIBM·Filed 2016·Granted Aug 28, 2018·4 cites·20 claims
- 0990US9116205B2Test coverage of integrated circuits with test vector input spreadingIBM·Filed 2012·Granted Aug 25, 2015·8 cites·8 claims
- 1089US8667431B1Test coverage of integrated circuits with masking pattern selectionIBM·Filed 2013·Granted Mar 4, 2014·6 cites·10 claims
- 1189US6735543B2Method and apparatus for testing, characterizing and tuning a chip interfaceIBM·Filed 2001·Granted May 11, 2004·48 cites·44 claims
- 1289US5617430ATesting system interconnections using dynamic configuration and test generationIBM·Filed 1993·Granted Apr 1, 1997·105 cites·19 claims
- 1387US9355203B2Shared channel masks in on-product test compression systemIBM·Filed 2014·Granted May 31, 2016·8 cites·8 claims
- 1484US9110135B2Chip testing with exclusive ORIBM·Filed 2013·Granted Aug 18, 2015·4 cites·13 claims
- 1584US8407542B2Implementing switching factor reduction in LBISTDOUSKEY STEVEN MICHAEL·Filed 2010·Granted Mar 26, 2013·8 cites·18 claims
- 1678US9032256B2Multi-core processor comparison encodingIBM·Filed 2013·Granted May 12, 2015·5 cites·19 claims
- 1777US7310278B2Method and apparatus for in-system redundant array repair on integrated circuitsIBM·Filed 2006·Granted Dec 18, 2007·8 cites·8 claims
- 1875US10372853B2Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)IBM·Filed 2017·Granted Aug 6, 2019·2 cites·18 claims
- 1974US8898530B1Dynamic built-in self-test systemIBM·Filed 2013·Granted Nov 25, 2014·4 cites·13 claims
- 2073US9746516B2Collecting diagnostic data from chipsIBM·Filed 2016·Granted Aug 29, 2017·1 cites·4 claims
- 2173US9285423B2Managing chip testing dataIBM·Filed 2013·Granted Mar 15, 2016·2 cites·15 claims
- 2273US9069041B2Self evaluation of system on a chip with multiple coresIBM·Filed 2012·Granted Jun 30, 2015·2 cites·19 claims
- 2373US7915929B2High-speed leaf clock frequency-divider/splitterIBM·Filed 2007·Granted Mar 29, 2011·6 cites·7 claims
- 2472US9297856B2Implementing MISR compression methods for test time reductionIBM·Filed 2013·Granted Mar 29, 2016·2 cites·9 claims
- 2572US5663966ASystem and method for minimizing simultaneous switching during scan-based testingIBM·Filed 1996·Granted Sep 2, 1997·34 cites·41 claims
- 2671US10067183B2Portion isolation architecture for chip isolation testIBM·Filed 2016·Granted Sep 4, 2018·2 cites·13 claims
- 2771US9575120B2Scan chain processing in a partially functional chipIBM·Filed 2013·Granted Feb 21, 2017·2 cites·1 claims
- 2871US7114109B2Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation featuresIBM·Filed 2004·Granted Sep 26, 2006·17 cites·20 claims
- 2970US7793184B2Lowering power consumption during logic built-in self-testing (LBIST) via channel suppressionIBM·Filed 2007·Granted Sep 7, 2010·5 cites·9 claims
- 3069US10024914B2Diagnosing failure locations of an integrated circuit with logic built-in self-testGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 17, 2018·1 cites·20 claims
- 3168US9726723B2Scan chain processing in a partially functional chipIBM·Filed 2015·Granted Aug 8, 2017·1 cites·15 claims
- 3267US6195775B1Boundary scan latch configuration for generalized scan designsIBM·Filed 1998·Granted Feb 27, 2001·27 cites·28 claims
- 3366US9372232B2Collecting diagnostic data from chipsIBM·Filed 2013·Granted Jun 21, 2016·1 cites·4 claims
- 3466US9151800B2Chip testing with exclusive ORIBM·Filed 2013·Granted Oct 6, 2015·1 cites·13 claims
- 3566US8516318B2Dynamic scanDOUSKEY STEVEN M·Filed 2010·Granted Aug 20, 2013·2 cites·19 claims
- 3664US9378318B2Shared channel masks in on-product test compression systemIBM·Filed 2014·Granted Jun 28, 2016·1 cites·8 claims
- 3763US6448835B1High-speed leaf splitter for clock gatingIBM·Filed 2001·Granted Sep 10, 2002·10 cites·15 claims
- 3862US8868975B2Testing and operating a multiprocessor chip with processor redundancyBELLOFATTO RALPH E·Filed 2011·Granted Oct 21, 2014·2 cites·25 claims
- 3961US11378623B2Diagnostic enhancement for multiple instances of identical structuresIBM·Filed 2020·Granted Jul 5, 2022·0 cites·18 claims
- 4061US11112854B2Operating pulsed latches on a variable power supplyIBM·Filed 2019·Granted Sep 7, 2021·0 cites·19 claims
- 4161US8365006B2Preventing circumvention of function disablement in an information handling systemIBM·Filed 2010·Granted Jan 29, 2013·1 cites·24 claims
- 4258US10816599B2Dynamically power noise adaptive automatic test pattern generationIBM·Filed 2019·Granted Oct 27, 2020·0 cites·20 claims
- 4358US9551747B2Inserting bypass structures at tap points to reduce latch dependency during scan testingIBM·Filed 2014·Granted Jan 24, 2017·0 cites·20 claims
- 4458US9529046B2Partitioned scan chain diagnostics using multiple bypass structures and injection pointsIBM·Filed 2014·Granted Dec 27, 2016·0 cites·13 claims
- 4558US9366723B2Test coverage of integrated circuits with masking pattern selectionGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 14, 2016·0 cites·6 claims
- 4657US9568549B2Managing redundancy repair using boundary scansIBM·Filed 2015·Granted Feb 14, 2017·0 cites·13 claims
- 4757US9557383B2Partitioned scan chain diagnostics using multiple bypass structures and injection pointsIBM·Filed 2014·Granted Jan 31, 2017·0 cites·20 claims
- 4857US9547039B2Inserting bypass structures at tap points to reduce latch dependency during scan testingIBM·Filed 2014·Granted Jan 17, 2017·0 cites·14 claims
- 4957US9134375B1Hierarchal test block test pattern reduction in on-product test compression systemIBM·Filed 2014·Granted Sep 15, 2015·0 cites·14 claims
- 5057US7949918B2Asynchronous communication using standard boundary architecture cellsIBM·Filed 2008·Granted May 24, 2011·1 cites·20 claims
Showing the top 50 of 80 patent records by PatentIndex Score.
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