Inventor · disambiguated record
Matthew S. Angyal
Also filed as: ANGYAL MATTHEW · ANGYAL MATTHEW S · ANGYAL MATTHEW STEPHEN
25 granted patents·13 pending applications·234 citations·filing 2002–2023
96Inventor score
Top patents by PatentIndex Score
38 records- 0195US8927442B1SiCOH hardmask with graded transition layersIBM·Filed 2013·Granted Jan 6, 2015·33 cites·10 claims
- 0293US8188574B2Pedestal guard ring having continuous M1 metal barrier connected to crack stopANGYAL MATTHEW S·Filed 2010·Granted May 29, 2012·21 cites·22 claims
- 0391US7325225B2Method and apparatus for reducing OPC model errorsTANAKA YASUSHI·Filed 2005·Granted Jan 29, 2008·17 cites·5 claims
- 0488US6917108B2Reliable low-k interconnect structure with hybrid dielectricIBM·Filed 2002·Granted Jul 12, 2005·49 cites·32 claims
- 0587US9455186B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Sep 27, 2016·4 cites·1 claims
- 0682US8237246B2Deep trench crackstops under contactsANGYAL MATTHEW S·Filed 2010·Granted Aug 7, 2012·7 cites·16 claims
- 0781US7093206B2Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structuresIBM·Filed 2003·Granted Aug 15, 2006·30 cites·28 claims
- 0880US7544609B2Method for integrating liner formation in back end of line processingIBM·Filed 2007·Granted Jun 9, 2009·9 cites·20 claims
- 0979US9385038B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Jul 5, 2016·2 cites·6 claims
- 1078US10796949B2Airgap vias in electrical interconnectsIBM·Filed 2018·Granted Oct 6, 2020·2 cites·20 claims
- 1177US7009280B2Low-k interlevel dielectric layer (ILD)IBM·Filed 2004·Granted Mar 7, 2006·15 cites·17 claims
- 1275US9859208B1Bottom self-aligned viaIBM·Filed 2016·Granted Jan 2, 2018·2 cites·20 claims
- 1374US8450212B2Method of reducing critical dimension process bias differences between narrow and wide damascene wiresANGYAL MATTHEW S·Filed 2011·Granted May 28, 2013·4 cites·25 claims
- 1473US7135398B2Reliable low-k interconnect structure with hybrid dielectricIBM·Filed 2004·Granted Nov 14, 2006·18 cites·28 claims
- 1571US8822342B2Method to reduce depth delta between dense and wide features in dual damascene structuresSRIVASTAVA RAVI PRAKASH·Filed 2010·Granted Sep 2, 2014·3 cites·18 claims
- 1670US8350359B2Semiconductor device using an aluminum interconnect to form through-silicon viasIBM·Filed 2009·Granted Jan 8, 2013·4 cites·16 claims
- 1767US9076847B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2013·Granted Jul 7, 2015·1 cites·6 claims
- 1865US7480605B2Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertaintyIBM·Filed 2005·Granted Jan 20, 2009·3 cites·21 claims
- 1964US7475368B2Deflection analysis system and method for circuit designIBM·Filed 2006·Granted Jan 6, 2009·3 cites·9 claims
- 2060US11011415B2Airgap vias in electrical interconnectsIBM·Filed 2020·Granted May 18, 2021·0 cites·20 claims
- 2159US2025062219A1Metal insulator metal capacitor (mim capacitor)IBM·Filed 2023·Application pending·0 cites
- 2259US2025072017A1Metal insulator metal capacitor (mim capacitor)IBM·Filed 2023·Application pending·0 cites
- 2358US2025006664A1Three dimensional mechanically bolting staple fillIBM·Filed 2023·Application pending·0 cites
- 2458US2025006663A1Double-sided integrated circuit with electrostatic guard ringIBM·Filed 2023·Application pending·0 cites
- 2558US2025006629A1Double-sided integrated circuit with damage sensorIBM·Filed 2023·Application pending·0 cites
- 2658US2025006590A1Double-sided integrated circuit with stabilizing cageIBM·Filed 2023·Application pending·0 cites
- 2757US2024429178A1Monolith structure for bspdn semiconductor devicesIBM·Filed 2023·Application pending·0 cites
- 2856US2025062218A1Metal insulator metal capacitor (mim capacitor)IBM·Filed 2023·Application pending·0 cites
- 2955US11663391B2Latch-up avoidance for sea-of-gatesIBM·Filed 2021·Granted May 30, 2023·0 cites·17 claims
- 3055US2024203816A1Heat dissipation structures for bonded wafersIBM·Filed 2022·Application pending·0 cites
- 3154US9406560B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Aug 2, 2016·0 cites·5 claims
- 3251US7214608B2Interlevel dielectric layer and metal layer sealingIBM·Filed 2004·Granted May 8, 2007·4 cites·20 claims
- 3347US6967158B2Method for forming a low-k dielectric structure on a substrateADVANCED MICRO DEVICES INC·Filed 2003·Granted Nov 22, 2005·3 cites·19 claims
- 3446US2008221849A1Method, Apparatus And Computer Program Product For Creating Electric Circuit Models Of Semiconductor Circuits From Fabrication Process ParametersANGYAL MATTHEW STEPHEN·Filed 2007·Application pending·0 cites
- 3546US2009031260A1Method, Computer Program and System Providing for Semiconductor Processes OptimizationANGYAL MATTHEW·Filed 2007·Application pending·0 cites
- 3644US12218120B2Device mismatch mitigation for medium range and beyond distancesIBM·Filed 2021·Granted Feb 4, 2025·0 cites·12 claims
- 3738US2009026587A1Gradient deposition of low-k cvd materialsIBM·Filed 2004·Application pending·0 cites
- 3831US2017170048A1Wafer handler for infrared laser releaseGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →