Inventor · disambiguated record
Steve Eaton
Also filed as: EATON STEVE · EATON STEVE S
7 granted patents·1 pending application·121 citations·filing 2002–2008
85Inventor score
Top patents by PatentIndex Score
8 records- 0192US7061823B2Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devicesPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jun 13, 2006·76 cites·23 claims
- 0269US7782080B2High capacitive load and noise tolerant system and method for controlling the drive strength of output drivers in integrated circuit devicesPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Granted Aug 24, 2010·6 cites·28 claims
- 0367US7349289B2Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAMPROMOS TECHNOLOGIES INC·Filed 2005·Granted Mar 25, 2008·5 cites·20 claims
- 0461US6721224B2Memory refresh methods and circuitsMOSEL VITELIC INC·Filed 2002·Granted Apr 13, 2004·12 cites·26 claims
- 0558US7071745B2Voltage-controlled analog delay locked loopPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jul 4, 2006·10 cites·21 claims
- 0651US7016235B2Data sorting in memoriesPROMOS TECHNOLOGIES PTE LTD·Filed 2004·Granted Mar 21, 2006·7 cites·30 claims
- 0746US7054215B2Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stagePROMOS TECHNOLOGIES PTE LTD·Filed 2004·Granted May 30, 2006·5 cites·21 claims
- 0840US2008137462A1Two-bit per i/o line write data bus for ddr1 and ddr2 operating modes in a dramPROMOS TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
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