Inventor · disambiguated record
Andreas Kuehlmann
Also filed as: KUEHLMANN ANDREAS
24 granted patents·1 pending application·477 citations·filing 1995–2022
96Inventor score
Top patents by PatentIndex Score
25 records- 0194US7624364B2Data path and placement optimization in an integrated circuit through use of sequential timing informationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 24, 2009·49 cites·4 claims
- 0292US7743354B2Optimizing integrated circuit design through use of sequential timing informationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 22, 2010·36 cites·33 claims
- 0390US7596770B1Temporal decomposition for design and verificationCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Sep 29, 2009·20 cites·11 claims
- 0490US6473884B1Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysisIBM·Filed 2000·Granted Oct 29, 2002·77 cites·21 claims
- 0587US9836390B2Static analysis of computer code to determine impact of change to a code component upon a dependent code componentSYNOPSYS INC·Filed 2015·Granted Dec 5, 2017·7 cites·32 claims
- 0687US7559040B1Optimization of combinational logic synthesis through clock latency schedulingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 7, 2009·22 cites·37 claims
- 0785US8307316B2Reducing critical cycle delay in an integrated circuit design through use of sequential slackALBRECHT CHRISTOPH·Filed 2011·Granted Nov 6, 2012·10 cites·38 claims
- 0884US9317399B2Policy evaluation based upon dynamic observation, static analysis and code change historySYNOPSYS INC·Filed 2013·Granted Apr 19, 2016·11 cites·43 claims
- 0984US6698003B2Framework for multiple-engine based verification tools for integrated circuitsIBM·Filed 2001·Granted Feb 24, 2004·38 cites·28 claims
- 1083US8418101B1Temporal decomposition for design and verificationKUEHLMANN ANDREAS·Filed 2011·Granted Apr 9, 2013·6 cites·19 claims
- 1182US9032376B2Static analysis of computer code to determine impact of change to a code component upon a dependent code componentSYNOPSYS INC·Filed 2013·Granted May 12, 2015·7 cites·32 claims
- 1282US7296246B1Multi-domain clock skew schedulingCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Nov 13, 2007·34 cites·38 claims
- 1381US9612943B2Prioritization of tests of computer program codeSYNOPSYS INC·Filed 2013·Granted Apr 4, 2017·7 cites·21 claims
- 1479US8656330B1Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and softwareKUEHLMANN ANDREAS·Filed 2010·Granted Feb 18, 2014·6 cites·15 claims
- 1579US7913210B2Reducing critical cycle delay in an integrated circuit design through use of sequential slackCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 22, 2011·9 cites·21 claims
- 1679US7900173B1Temporal decomposition for design and verificationCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Mar 1, 2011·7 cites·14 claims
- 1778US8589845B2Optimizing integrated circuit design through use of sequential timing informationALBRECHT CHRISTOPH·Filed 2009·Granted Nov 19, 2013·9 cites·14 claims
- 1878US6035107AMethod for performing functional comparison of combinational circuitsIBM·Filed 1997·Granted Mar 7, 2000·86 cites·20 claims
- 1973US8020125B1System, methods and apparatus for generation of simulation stimulusCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Sep 13, 2011·10 cites·24 claims
- 2070US8862439B1General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and softwareKUEHLMANN ANDREAS·Filed 2010·Granted Oct 14, 2014·3 cites·20 claims
- 2165US8413090B1Temporal decomposition for design and verificationKUEHLMANN ANDREAS·Filed 2011·Granted Apr 2, 2013·1 cites·16 claims
- 2262US10713069B2Software and hardware emulation systemSYNOPSYS INC·Filed 2016·Granted Jul 14, 2020·1 cites·20 claims
- 2357US5629858ACMOS transistor network to gate level model extractor for simulation, verification and test generationIBM·Filed 1995·Granted May 13, 1997·21 cites·2 claims
- 2451US12387021B2Using information flow for security aware design and analysisCYCUITY INC·Filed 2022·Granted Aug 12, 2025·0 cites·20 claims
- 2542US2023394158A1Using Information Flow For Security Exploration and AnalysisTORTUGA LOGIC INC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →