Inventor · disambiguated record
Martin G. Dixon
Also filed as: DIXON MARTIN · DIXON MARTIN G · DIXON MARTIN GUY
128 granted patents·17 pending applications·485 citations·filing 1996–2023
99Inventor score
Top patents by PatentIndex Score
145 records- 0197US9235414B2SIMD integer multiply-accumulate instruction for multi-precision arithmeticGOPAL VINODH·Filed 2011·Granted Jan 12, 2016·53 cites·21 claims
- 0297US8538015B2Flexible architecture and instruction for advanced encryption standard (AES)GUERON SHAY·Filed 2007·Granted Sep 17, 2013·40 cites·23 claims
- 0395US9960917B2Matrix multiply accumulate instructionGOPAL VINODH·Filed 2011·Granted May 1, 2018·39 cites·24 claims
- 0495US8301849B2Transactional memory in out-of-order processors with XABORT having immediate argumentRAJWAR RAVI·Filed 2009·Granted Oct 30, 2012·40 cites·20 claims
- 0593US8447962B2Gathering and scattering multiple data elementsHUGHES CHRISTOPHER J·Filed 2009·Granted May 21, 2013·36 cites·30 claims
- 0691US8464035B2Instruction for enabling a processor wait stateDIXON MARTIN G·Filed 2009·Granted Jun 11, 2013·23 cites·24 claims
- 0790US10409612B2Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·7 cites·20 claims
- 0887US10256971B2Flexible architecture and instruction for advanced encryption standard (AES)INTEL CORP·Filed 2015·Granted Apr 9, 2019·2 cites·14 claims
- 0986US11106461B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2018·Granted Aug 31, 2021·2 cites·24 claims
- 1086US9772845B2Method and apparatus to process KECCAK secure hashing algorithmYAP KIRK S·Filed 2011·Granted Sep 26, 2017·8 cites·20 claims
- 1186US9747105B2Method and apparatus for performing a shift and exclusive or operation in a single instructionGOPAL VINODH·Filed 2009·Granted Aug 29, 2017·11 cites·39 claims
- 1286US8489660B2Digital random number generator using partially entropic dataHERBERT HOWARD C·Filed 2009·Granted Jul 16, 2013·24 cites·17 claims
- 1385US8700943B2Controlling time stamp counter (TSC) offsets for mulitple cores and threadsDIXON MARTIN G·Filed 2009·Granted Apr 15, 2014·14 cites·24 claims
- 1485US8538012B2Performing AES encryption or decryption in multiple modes with a single instructionDIXON MARTIN·Filed 2007·Granted Sep 17, 2013·15 cites·16 claims
- 1584US10152326B2Method and apparatus to process SHA-2 secure hashing algorithmINTEL CORP·Filed 2016·Granted Dec 11, 2018·4 cites·34 claims
- 1684US9940131B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Apr 10, 2018·4 cites·28 claims
- 1784US9940130B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Apr 10, 2018·4 cites·22 claims
- 1884US9916160B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Mar 13, 2018·4 cites·20 claims
- 1984US9740484B2Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storageGOPAL VINODH·Filed 2011·Granted Aug 22, 2017·8 cites·12 claims
- 2084US9632782B2Method and apparatus to process SHA-2 secure hashing algorithmYAP KIRK S·Filed 2012·Granted Apr 25, 2017·7 cites·21 claims
- 2183US11550582B2Method and apparatus to process SHA-2 secure hashing algorithmINTEL CORP·Filed 2020·Granted Jan 10, 2023·1 cites·18 claims
- 2283US9495166B2Method and apparatus for performing a shift and exclusive or operation in a single instructionINTEL CORP·Filed 2014·Granted Nov 15, 2016·4 cites·27 claims
- 2382US10235175B2Processors, methods, and systems to relax synchronization of accesses to shared memoryINTEL CORP·Filed 2016·Granted Mar 19, 2019·3 cites·18 claims
- 2481US10725779B2Method and apparatus to process SHA-2 secure hashing algorithmINTEL CORP·Filed 2019·Granted Jul 28, 2020·1 cites·11 claims
- 2581US9164762B2Rotate instructions that complete execution without reading carry flagINTEL CORP·Filed 2013·Granted Oct 20, 2015·4 cites·31 claims
- 2680US9501281B2Method and apparatus for performing a shift and exclusive or operation in a single instructionINTEL CORP·Filed 2014·Granted Nov 22, 2016·3 cites·27 claims
- 2780US9411600B2Instructions and logic to provide memory access key protection functionalityINTEL CORP·Filed 2013·Granted Aug 9, 2016·4 cites·41 claims
- 2879US8738893B2Add instructions to add three source operandsINTEL CORP·Filed 2013·Granted May 27, 2014·5 cites·20 claims
- 2979US8635415B2Managing and implementing metadata in central processing unit using register extensionsPATEL BAIJU V·Filed 2009·Granted Jan 21, 2014·11 cites·13 claims
- 3079US8392657B2Monitoring cache usage in a distributed shared cacheZHAO LI·Filed 2009·Granted Mar 5, 2013·10 cites·17 claims
- 3178US10684855B2Method and apparatus for performing a shift and exclusive or operation in a single instructionINTEL CORP·Filed 2017·Granted Jun 16, 2020·1 cites·19 claims
- 3278US9544139B2Method and apparatus for a non-deterministic random bit generator (NRBG)COX GEORGE W·Filed 2011·Granted Jan 10, 2017·7 cites·8 claims
- 3378US8990597B2Instruction for enabling a processor wait stateINTEL CORP·Filed 2013·Granted Mar 24, 2015·3 cites·20 claims
- 3478US7500049B2Providing a backing store in user-level memoryINTEL CORP·Filed 2005·Granted Mar 3, 2009·8 cites·26 claims
- 3577US8549264B2Add instructions to add three source operandsGOPAL VINODH·Filed 2009·Granted Oct 1, 2013·6 cites·30 claims
- 3677US8504807B2Rotate instructions that complete execution without reading carry flagGOPAL VINODH·Filed 2009·Granted Aug 6, 2013·4 cites·22 claims
- 3776US10469557B2QoS based binary translation and application streamingINTEL CORP·Filed 2016·Granted Nov 5, 2019·2 cites·14 claims
- 3876US10331451B2Method and apparatus to process SHA-2 secure hashing algorithmINTEL CORP·Filed 2016·Granted Jun 25, 2019·1 cites·31 claims
- 3976US10127042B2Method and apparatus to process SHA-2 secure hashing algorithmINTEL CORP·Filed 2016·Granted Nov 13, 2018·1 cites·14 claims
- 4076US8929539B2Instructions to perform Groestl hashingWOLRICH GILBERT M·Filed 2011·Granted Jan 6, 2015·4 cites·28 claims
- 4176US8214598B2System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entriesDIXON MARTIN G·Filed 2009·Granted Jul 3, 2012·7 cites·13 claims
- 4275US11900108B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2021·Granted Feb 13, 2024·0 cites·19 claims
- 4375US9304940B2Processors, methods, and systems to relax synchronization of accesses to shared memoryINTEL CORP·Filed 2013·Granted Apr 5, 2016·3 cites·16 claims
- 4475US8913740B2Method and apparatus for generating an Advanced Encryption Standard (AES) key scheduleINTEL CORP·Filed 2013·Granted Dec 16, 2014·3 cites·20 claims
- 4572US11531542B2Addition instructions with independent carry chainsINTEL CORP·Filed 2021·Granted Dec 20, 2022·0 cites·18 claims
- 4672US11080045B2Addition instructions with independent carry chainsGOPAL VINODH·Filed 2011·Granted Aug 3, 2021·2 cites·16 claims
- 4772US9325498B2Performing AES encryption or decryption in multiple modes with a single instructionINTEL CORP·Filed 2013·Granted Apr 26, 2016·2 cites·21 claims
- 4872US8954754B2Method and apparatus to process SHA-1 secure hashing algorithmYAP KIRK S·Filed 2011·Granted Feb 10, 2015·3 cites·20 claims
- 4971US9203887B2Bitstream processing using coalesced buffers and delayed matching and enhanced memory writesGOPAL VINODH·Filed 2011·Granted Dec 1, 2015·5 cites·18 claims
- 5070US9495165B2Method and apparatus for performing a shift and exclusive or operation in a single instructionINTEL CORP·Filed 2014·Granted Nov 15, 2016·1 cites·33 claims
Showing the top 50 of 145 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →