Inventor · disambiguated record
Bidyut K. Bhattacharyya
Also filed as: BHATTACHARYYA BIDYUT · BHATTACHARYYA BIDYUT K
22 granted patents·901 citations·filing 1987–2003
97Inventor score
Top patents by PatentIndex Score
22 records- 0196US4891687AMulti-layer molded plastic IC packageINTEL CORP·Filed 1989·Granted Jan 2, 1990·170 cites·10 claims
- 0293US5210939ALead grid array integrated circuitINTEL CORP·Filed 1992·Granted May 18, 1993·141 cites·21 claims
- 0393US4835120AMethod of making a multilayer molded plastic IC packageMALLIK DEBENDRA·Filed 1988·Granted May 30, 1989·118 cites·2 claims
- 0485US5608261AHigh performance and high capacitance package with improved thermal dissipationINTEL CORP·Filed 1994·Granted Mar 4, 1997·68 cites·9 claims
- 0582US5369545ADe-coupling capacitor on the top of the silicon die by eutectic flip bondingINTEL CORP·Filed 1993·Granted Nov 29, 1994·90 cites·4 claims
- 0672US5666004AUse of tantalum oxide capacitor on ceramic co-fired technologyINTEL CORP·Filed 1996·Granted Sep 9, 1997·41 cites·3 claims
- 0771US5420461AIntegrated circuit having a two-dimensional lead grid arrayINTEL CORP·Filed 1994·Granted May 30, 1995·37 cites·3 claims
- 0862US5607883AHigh performance and high capacitance package with improved thermal dissipationINTEL CORP·Filed 1996·Granted Mar 4, 1997·23 cites·10 claims
- 0962US5488257AMultilayer molded plastic package using mesic technologyINTEL CORP·Filed 1995·Granted Jan 30, 1996·24 cites·10 claims
- 1061US5556807AAdvance multilayer molded plastic package using mesic technologyINTEL CORP·Filed 1993·Granted Sep 17, 1996·26 cites·29 claims
- 1160US5475565APower distribution lid for IC packageINTEL CORP·Filed 1994·Granted Dec 12, 1995·30 cites·13 claims
- 1255US5773895AAnchor provisions to prevent mold delamination in an overmolded plastic array packageINTEL CORP·Filed 1996·Granted Jun 30, 1998·26 cites·13 claims
- 1353US5099388AAlumina multilayer wiring substrate provided with high dielectric material layerNGK SPARK PLUG CO·Filed 1990·Granted Mar 24, 1992·24 cites·12 claims
- 1451US6664620B2Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layerINTEL CORP·Filed 1999·Granted Dec 16, 2003·16 cites·18 claims
- 1550US5307012ATest substation for testing semi-conductor packagesINTEL CORP·Filed 1993·Granted Apr 26, 1994·17 cites·34 claims
- 1648US4810671AProcess for bonding die to substrate using a gold/silicon seedINTEL CORP·Filed 1988·Granted Mar 7, 1989·15 cites·2 claims
- 1747US7030479B2Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layerINTEL CORP·Filed 2003·Granted Apr 18, 2006·3 cites·14 claims
- 1839US5777265AMultilayer molded plastic package designINTEL CORP·Filed 1997·Granted Jul 7, 1998·13 cites·6 claims
- 1936US4771018AProcess of attaching a die to a substrate using gold/silicon seedINTEL CORP·Filed 1987·Granted Sep 13, 1988·7 cites·3 claims
- 2031US5532983ACircuit design for point-to-point chip for high speed testingINTEL CORP·Filed 1992·Granted Jul 2, 1996·4 cites·8 claims
- 2131US5345363AMethod and apparatus of coupling a die to a lead frame with a tape automated bonded tape that has openings which expose portions of the tape leadsINTEL CORP·Filed 1993·Granted Sep 6, 1994·2 cites·7 claims
- 2229US5060049AMultiple resistivity wiring apparatusNGK SPARK PLUG CO·Filed 1990·Granted Oct 22, 1991·6 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →