Inventor · disambiguated record
Jason L. Frankel
Also filed as: FRANKEL JASON · FRANKEL JASON L · FRANKEL JASON LEE
18 granted patents·2 pending applications·145 citations·filing 1996–2024
93Inventor score
Top patents by PatentIndex Score
20 records- 0191US7806341B2Structure for implementing secure multichip modules for encryption applicationsIBM·Filed 2009·Granted Oct 5, 2010·16 cites·26 claims
- 0291US7281667B2Method and structure for implementing secure multichip modules for encryption applicationsIBM·Filed 2005·Granted Oct 16, 2007·18 cites·4 claims
- 0389US7348667B2System and method for noise reduction in multi-layer ceramic packagesIBM·Filed 2005·Granted Mar 25, 2008·17 cites·20 claims
- 0485US7472836B2Method and structure for implementing secure multichip modules for encryption applicationsIBM·Filed 2007·Granted Jan 6, 2009·11 cites·5 claims
- 0582US11775004B2Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die moduleIBM·Filed 2021·Granted Oct 3, 2023·1 cites·8 claims
- 0681US8927879B2Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structuresCHOI JINWOO·Filed 2010·Granted Jan 6, 2015·4 cites·7 claims
- 0772US12111684B2Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die moduleIBM·Filed 2023·Granted Oct 8, 2024·0 cites·8 claims
- 0869US9955567B2Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structuresIBM·Filed 2014·Granted Apr 24, 2018·1 cites·10 claims
- 0969US5831810AElectronic component package with decoupling capacitors completely within die receiving cavity of substrateIBM·Filed 1996·Granted Nov 3, 1998·41 cites·17 claims
- 1066US6762489B2Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modulesIBM·Filed 2001·Granted Jul 13, 2004·12 cites·14 claims
- 1162US10949600B2Semiconductor package floating metal checksIBM·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 1260US2025285965A1Pinwheel-shaped connections between diagonally opposite integrated circuits in a multi-chip module to reduce number of routing layersIBM·Filed 2024·Application pending·0 cites
- 1356US10423751B2Semiconductor package floating metal checksIBM·Filed 2017·Granted Sep 24, 2019·0 cites·20 claims
- 1454US10375820B2Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structuresIBM·Filed 2018·Granted Aug 6, 2019·0 cites·7 claims
- 1550US6974722B2Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modulesIBM·Filed 2004·Granted Dec 13, 2005·4 cites·3 claims
- 1647US10706204B2Automated generation of surface-mount package designIBM·Filed 2018·Granted Jul 7, 2020·0 cites·17 claims
- 1747US7096451B2Mesh plane generation and file storageIBM·Filed 2003·Granted Aug 22, 2006·5 cites·28 claims
- 1847US2007080436A1System and Method for Noise Reduction in Multi-Layer Ceramic PackagesIBM·Filed 2006·Application pending·0 cites
- 1945US5946552AUniversal cost reduced substrate structure method and apparatusIBM·Filed 1996·Granted Aug 31, 1999·15 cites·20 claims
- 2039US7325213B2Nested design approachIBM·Filed 2005·Granted Jan 29, 2008·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →